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Primitive quantum gates: (A) NOT; (B) CNOT; (C) Controlled V; (D) Controlled V⁺; and (E) integrated qubit
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Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits d...
Citations
... In a ripple carry adder, each bit's carry depends on the previous bit, causing a sequential carry propagation through the entire adder. This leads to increased propagation delay, limiting the overall performance of the adder, especially for larger bit-widths [30][31][32][33]. In contrast, a carry look-ahead adder utilizes parallelism by precomputing the carry signals independently of the input bits. ...
... Reversible logic is a computing paradigm that has gained significant attention recently due to its potential for low-power and quantum computing applications. 20 Remarkably, the Toffoli gate holds the status of universality in classical reversible computation, implying that any reversible computation can be constructed by employing a combination of Toffoli gates. Reversible logic boasts a multitude of potential applications, particularly in burgeoning technologies. ...
... In the realm of classical computing, reversible logic stands out for its ability to design circuits with markedly reduced power consumption, a critical factor for mobile and embedded systems. 20 Furthermore, reversible logic gates assume a pivotal role as foundational components for designing quantum algorithms in quantum computing, where the preservation of quantum states stands as a paramount imperative. 20 ...
Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.
... Quantum circuits for arithmetic operations as the vital part of a quantum computer's reversible arithmetic logic unit can be realized by quantum gates [8,9]. For instance, Noorallahzadeh et al. used elementary quantum gates in the NCV (NOT, CNOT, Controlled-V, and Controlled-V+) library to design quantum multipliers [10][11][12]. These multipliers have the low quantum cost, garbage output, and constant input. ...
Quantum circuits for multiplication and division are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant realizations. T gates are more expensive than other gates in Clifford + T circuits. But neglecting the cost of CNOT gates may lead to a significant underestimation. Moreover, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. As a result, reducing T-count, T-depth, CNOT-count, CNOT-depth, and circuit width has become the important optimization goal. We use 3-bit Hermitian gates to design basic arithmetic operations. Then, we present a special multiplier and a divider using basic arithmetic operations, where ‘special’ means that one of the two operands of multiplication is non-zero. Next, we use new rules to optimize the Clifford + T circuits of the special multiplier and divider in terms of T-count, T-depth, CNOT-count, CNOT-depth, and circuit width. Comparative analysis shows that the proposed multiplier and divider have lower T-count, T-depth, CNOT-count, and CNOT-depth than the current works. For instance, the proposed 32-bit divider achieves improvement ratios of 40.41 percent, 31.64 percent, 45.27 percent, and 65.93 percent in terms of T-count, T-depth, CNOT-count, and CNOT-depth compared to the best current work. Further, the circuit widths of the proposed n-bit multiplier and divider are 3n. I.e., our multiplier and divider reach the minimum width of multipliers and dividers, keeping an operand unchanged.
... Reversible logic is a unique type of computation in which the relationship between input and output vectors is entirely reversible. 18 This means that given the output, one can retrieve the original input data without any loss of information or energy. This characteristic is a fundamental aspect of n × n reversible gates or circuits. ...
Quantum Dot Cellular Automata (QCA) and reversible logic have emerged as promising alternatives to conventional CMOS technology, offering several advantages, such as ultra-dense structures and ultra-low-power consumption. Among the crucial components of processors, the Arithmetic Logic Unit (ALU) has witnessed significant advancements in reversible computing, leading to energy-efficient and high-speed computing systems, particularly beneficial for Digital Signal Processing (DSP) applications. Conventional ALUs, reliant on irreversible logic, encounter energy inefficiencies due to information loss during computations, resulting in increased power consumption. Moreover, they may face limitations in processing speed, impacting real-time processing capabilities, especially for complex DSP tasks involving intensive arithmetic and logic operations. In response to these challenges, a research paper presents a pioneering approach, proposing a novel reversible ALU design using QCA nanotechnology. The proposed design ingeniously incorporates Modified Fredkin (MF) gates, and a coplanar reversible full adder based on the HNG gate, skillfully leveraging the unique features of QCA nanotechnology to optimize the ALU's energy-efficient and high-speed performance for DSP applications. This revolutionary QCA reversible ALU comprises 330 QCA cells arranged in a compact 0.41 μm2 area, skillfully realized through the coplanar clock-zone-based crossover approach. Its core computational elements, the three MF gates, and the innovative coplanar reversible full adder empower the ALU to execute a remarkable array of 20 distinct arithmetic and logic operations, showcasing its versatility in handling diverse DSP tasks. The proposed structure undergoes extensive simulations utilizing QCADesigner version 2.0.3 to confirm its performance. The evaluation results manifest substantial improvements compared to previous designs, boasting a 30% reduction in area occupancy, a 20% decrement in cell count, a 10% reduction in latency, and a 10% decrease in quantum cost compared to the best-known previous structure. These compelling outcomes solidify the potential of the proposed reversible ALU as a transformative advancement in energy-efficient and high-speed computing for DSP applications.
... Template matching with inputs and outputs is a standard process in quantum circuits [29]. The template matching approach reduces quantum costs. ...
... The tensor products of one-qubit states create the computational foun- dation for two-qubit states. It is only with the increase in qubits that quantum computing is revealed to its full potential [29]. This powerful functionality can be achieved because the quantum state vector space has an exponential expansion with the number of qubits. ...
In nano communication, fault-tolerant networks play a crucial role in error control. A significant practical challenge for nanocircuits is their ability to transmit information over networks to different endpoints. Fault-tolerant and reversible circuits have control error problems. The advantage of a quantum gate-based architecture is that it prevents heat loss, and it has been extensively researched. In this article, we have developed reversible multiplexers (mux's), half-adder (HA), and full-adder (FA) and latches that are fault-tolerant by making use of new gate and implementing them on the IBM Qiskit platform. A power-efficient and fault-tolerant mux's and latches is proposed that uses reversible gates to preserve parity. Multiplexer kinds such as 2:1, 4:1, and n:1 is covered in depth by the new Parity Preserving Multiplexer (PPM) gate and verified by IBM-Qiskit. An algorithmic design for an n:1 multiplexer is invented. In order to assess a PPM gate effectiveness, 13 standard Boolean functions and 8 standard types of gates are implemented. The PPM quantum gate is built using quantum assembly code (QAC), which runs on IBM Quantum Lab and IBM Quantum Composer platforms to measure the output qubits. Additional HA, muxes, and latches design led to the code creation in the Qiskit platform, which was used to measure the output qubits. A comparison of the D-latch, T-latch, JK-latch, and mux designs with existing circuits shows a reduction in quantum cost (qc) and junk output (go) and the implementation of a custom design in the IBM-Qiskit platform to measure output qubits is a first time in literature.
... In IC technology, energy dissipation is one of the most vital factors [9]. Energy loss in a system is proportional to the number of bits lost during logical computation [10]. The irreversible technology will dissipate the loss of heat [11]. ...
The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs.
... Reversible computing is utilised in a variety of sectors, including smart city technology, optical computing, nanotechnology, the biomedical industry, and amongst others [7][8][9]. To synthesize a suitable reversible circuit, the designed circuit must have the lowest garbage output (GO), constant input (CI), and quantum cost (QC) [4,[9][10][11]. The cost, which refers to the counting of (1 × 1 and 2 × 2) elementary quantum gates, is frequently used to determine implementation quantum costs. The quantum cost of any (1 × 1 and 2 × 2) gates is equal to one. ...
... The (m + n) bit product can be expressed as shown in Eqs. (10)(11)(12): ...
As a result of the recent development of quantum computers, there has been a rise in interest in both reversible logic synthesis and optimization strategies. Because every quantum operation is intrinsically reversible, there is a significant desire for research to create and optimize reversible circuits. This work suggests two novel reversible blocks with a low quantum cost. The reversible blocks are synthesized by an available synthesis technique that produces a grid list of multiple-control Toffoli gates. Then, the Toffoli-based grid is subjected to various optimization techniques, after which it is converted into a netlist of elementary quantum gates taken from the NCV (NOT, CNOT, Controlled-V, and Controlled-V⁺) library. In addition, a suggestion is presented for the creation of an unsigned multiplier that makes use of the functional blocks that are already available in the system. It has been found that the suggested designs are superior in terms of reversible metrics compared to the most cutting-edge techniques. Compared to recent works, the unsigned multiplier results in average savings of 14.43% for the quantum cost, 27.34% for the garbage output, and 23.29% for the constant input.
Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.
