Fig 15 - uploaded by M. Kosunen
Content may be subject to copyright.
Source publication
A global system for mobile communication (GSM)/enhanced data rates for GSM evolution (EDGE)/wideband code division multiple access (WCDMA) modulator with a 14-bit on-chip digital-to-analog (D/A) converter is presented. The modulator consists of several digital signal processing building blocks, including a programmable pulse shaping filter, interpo...
Similar publications
WRC-2000 has identified additional bands 806-960 MHz, 1710-1885 MHz, and 2500-2690 MHz for possible use by IMT-2000 systems. In relation to 2.5 GHz band (2500-2690 MHz), ITU-WP8F has defined seven possible scenarios for the frequency arrangements. These scenarios include the operation of FDD DL only, paired FDD UL/DL or TDD or combinations of them...
In this paper, the three radio access technologies which have been chosen for the UMTS are evaluated both, by analytical calculations and by means of dynamic simulation. The most famous mode WCDMA or UTRA-FDD is compared to the two TDD modes with 3.84 Mcps (also known as TD-CDMA) and 1.28 Mcps which was developed based on the Chinese TD-SCDMA. A mu...
The deployment of third generation CDMA-based wireless systems
foresees a loading fraction that is smaller than one, i.e. the number of
users per cell is scheduled to be significantly less than the spreading
factor to attain an acceptable performance. This means that a base
station can set apart a subset of the codes, the excess codes, that it
will...
Citations
... A traditional way of transmitting these data is depicted in Fig. 1, using oversampled digital-to-analog converters followed by low-pass filters to reject the image replicas and respect the required transmission masks. To address multistandard within the same hardware, a direct-digital RF modulator was proposed in [3] programmable sample rate converters, as proposed in [4] and [5], to adapt to the appropriate radio channel. ...
This paper presents a novel transmitter architecture which is tailored for low power, all-digital, and high speed implementation. It is based on two-path parallel digital-to-analog converters (DAC) which are driven by 180 ° phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a low-pass ΔΣ-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear digital-to-analog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the ΔΣ-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below -22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-digital transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes. IEEE
... A traditional way of transmitting these data is depicted in Fig. 1, using oversampled digital-to-analog converters followed by low-pass filters to reject the image replicas and respect the required transmission masks. To address multistandard within the same hardware, a direct-digital RF modulator was proposed in [3] programmable sample rate converters, as proposed in [4] and [5], to adapt to the appropriate radio channel. ...
IEEE 802.11ac (WiFi) and IEEE 802.11ad (60-GHz WiGig) are emerging gigabit-per-second standards providing complementary services but different nature of signals. The 802.11ac targets high-resolution and narrow-to-medium bandwidth channels, while 802.11ad aims to provide broadband communications with simple modulation schemes. This work proposes a single-physical-layer transmitter baseband architecture for both 11ac and 11ad standards. The core of the proposed transmitter is a configurable mixed-signal digital-to-analog converter (DAC), which has an embedded semidigital filtering tailored for four WiFi modes (20, 40, 80, and 160 MHz) and the 1.76-GHz bandwidth of the 60-GHz WiGig standard. The DAC operates on the oversampled WiFi and raw WiGig data at a common 3.52-GHz clock frequency. System-level simulations of the finite impulse response DAC-based architecture show that the requirements of the standards can be met with maximum hardware sharing and reduced area penalty.
... The desired signal is an IQ modulated complex signal. Digital tel-00280968, version 1 -20 May 2008 processing blocks ensure its shaping [34,35]. Then, data scrambling allows separating users by assigning each one a different code and thus controls confidentiality of transmitted data [36]. ...
Dans le cadre de la radio logicielle, un transmetteur numérique, basé sur la modulation ΔΣ, est proposé. Son architecture est construite autour de deux modulateurs ΔΣ passe-bas suréchantillonnés du 3ème ordre qui fournissent un signal multiplexé sur 1 bit à haute cadence, qui code directement le signal RF dans le domaine numérique. La séquence de sortie peut ensuite être appliquée à l’entrée d’un amplificateur de puissance commuté ayant une bonne efficacité.
Le standard UMTS a été choisi comme exemple d’application et un générateur de signaux RF 1 bit à 7,8Géch/s a été réalisé dans une technologie 90nm CMOS. Une arithmétique redondante comprenant des signaux complémentaires, une quantification de sortie non exacte et une évaluation anticipée de la sortie ont été implémentées pour parvenir à la cadence désirée. Une logique dynamique différentielle sur 3 phases d’horloge, générées par une DLL, a été utilisée au niveau circuit.
Le circuit intégré du transmetteur prototype démontre une fonctionnalité complète jusqu’à une fréquence d’horloge de 4GHz, permettant ainsi d’atteindre une bande passante de 50MHz autour d’une fréquence porteuse de 1GHz. Si la bande image est utilisée, la fréquence d’émission peut être déplacée jusqu’à 3GHz. Avec une fréquence d’horloge de 2,6GHz et un canal WCDMA de 5MHz modulé autour d’une fréquence porteuse à 650MHz, 53,6dB d’ACLR sont obtenus pour une puissance de canal en sortie de -3,9dBm. Pour la bande image (1,95GHz), l’ACPR est de 44,3dB pour une puissance maximale du canal en sortie de -15,8dBm, ce qui rentre dans les spécifications UMTS. L’aire active du circuit est de 0,15mm² et sa consommation de 69mW sous 1V à cette fréquence.
... The double lines connecting different blocks indicate that there are two identical datapaths for both inphase path and quadrature path (I and Q). In a traditional modulator, a quadrature direct digital frequency synthesizer (QDDFS) will be used to modulate the signal to intermediate frequency (IF), and then the digital output is converted to analog signal using DAC [1,15]. In the all-digital transmitter presented in this paper, an RFPWM will be used to directly synthesize RF signals in digital domain. ...
... A different control approach is to use the MSB of the NCO register as the reference clock for the delay line as shown in Figure 6. This reference clock is further divided down to provide sample rate clocks to the different interpolation filters inside the multi-stage upsampling filters [1,15]. The novelty of our implementation only requires one system clock for all the filter stages. ...
... The screen shots for spectrum and EVM measurements are shown in Figure 12. In the 20 MHz passband, the measured ACLR is 45 dB, which can meet the requirement for WCDMA [15]. The noise shaping effects can clearly be seen from the spectrum plot where the noise rises outside the RF signal bandwidth. ...
This paper presents the architecture and implementation of an all-digital transmitter with radio frequency output targeting an FPGA device. FPGA devices have been widely adopted in the applications of digital signal processing (DSP) and digital communication. They are typically well suited for the evolving technology of software defined radios (SDR) due to their reconfigurability and programmability. However, FPGA devices are mostly used to implement digital baseband and intermediate frequency (IF) functionalities. Therefore, significant analog and RF components are still needed to fulfill the radio communication requirements. The all-digital transmitter presented in this paper directly synthesizes RF signal in the digital domain, therefore eliminates the need for most of the analog and RF components. The all-digital transmitter consists of one QAM modulator and one RF pulse width modulator (RFPWM). The binary output waveform from RFPWM is centered at 800MHz with 64QAM signaling format. The entire transmitter is implemented using Xilinx Virtex2pro device with on chip multi-gigabit transceiver (MGT). The adjacent channel leakage ratio (ACLR) measured in the 20 MHz passband is 45dB, and the measured error vector magnitude (EVM) is less than 1%. Our work extends the digital implementation of communication applications on an FPGA platform to radio frequency, therefore making a significant evolution towards an ideal SDR
... In conventional GSM base station solutions, transmitted carriers are combined in the analogue domain after the power amplifiers by a lossy RF combiner. An alternative method is to combine the carriers in the digital domain [1,2] that provides a number of benefits over the conventional solution. It saves a large number of analogue components, and there is no need for cavity or hybrid combiners. ...
... Equation (1) shows that a baseband signal has only two different levels {À1, 1}. After the spreading operation the signals intended for different users are weighted and added together according to ...
In conventional GSM base station solutions, transmitted carriers are combined after power amplifiers. A GSM signal is a constant envelope signal which means that a power efficient nonlinear power amplifier can be used. However, in third generation systems the signal is no longer a constant envelope signal, which means that linearity requirements for the PA are increased. Also, in the case of multicarrier GSM or EDGE transmission the peak to average power of the signal becomes high if the carriers are combined in the digital domain. High linearity requirements lead to low power efficiency and therefore to high power consumption. In order to achieve good efficiency in the PA the PAR must be reduced, i.e. the signal must be clipped. In the paper the effect of a peak windowing clipping algorithm is studied in the cases of WCDMA, GSM and EDGE transmission. Also, an efficient way to implement the peak windowing algorithm is presented.
... The digital quadrature modulator is fed by two digital complex modulators, shown in Fig. 2, which modulate the baseband in-phase (I) and quadrature (Q) channels into orthogonal carriers (X, Y ) at the first IF frequency. One example of such a complex modulator suitable for this purpose is presented in [1]. These complex modulators can be operated at a much lower sampling frequency than the quadrature modulator. ...
A digital quadrature modulator with a bandpass ΔΣ-modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f
s
/4, −f
s
/4 (f
s
is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass ΔΣ modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm2 (0.13 μm CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).
... Due to the relatively low sampling frequency needed in this block, most of the programmability is easiest to implement in this block. A multimode modulator suitable for this system is presented in [1]. The purpose of the digital upmixer is simply to increase the sampling rate and to upmix the signal to the desired RF frequency. ...
In this paper a concept of a transmitter using delta-sigma modulation and switching mode power amplifier is presented. The specifications of a WCDMA base station transmitter are as an objective. Using a delta-sigma modulation in a D/A conversion, most of the nonlinearities of a multi-bit D/A converter are avoided. In addition the 1-bit output signal of the delta-sigma modulator is suitable for power efficient switching mode power amplifiers. The use of the images of the signal is studied as a method to reduce the required sampling frequency. The problems and possible solutions in implementing a wideband transmitter with this topology are discussed as well.
... The first analog IF mixer stage of the transmitter can be replaced with this digital quadrature modulator as shown in Fig. 1. In two-stage upconversions, two complex modulators are in series with the quadrature modulator as shown in Fig. 2. In the digital complex modulators [1], [2], the baseband in-phase (I) and quadrature (Q) channels are modulated onto orthogonal carriers at the IF frequency at the lower sampling rate. The tunable complex modulator, steered by the carrier NCO, enables the fine tuning of the transmitted carrier frequency with sub-Hz resolution [1], [2], whereas this digital quadrature modulator is used for the coarse tuning. ...
... In two-stage upconversions, two complex modulators are in series with the quadrature modulator as shown in Fig. 2. In the digital complex modulators [1], [2], the baseband in-phase (I) and quadrature (Q) channels are modulated onto orthogonal carriers at the IF frequency at the lower sampling rate. The tunable complex modulator, steered by the carrier NCO, enables the fine tuning of the transmitted carrier frequency with sub-Hz resolution [1], [2], whereas this digital quadrature modulator is used for the coarse tuning. It is advantageous to implement the fine tuning at lower sampling frequencies and the coarse tuning at the higher frequencies, because of the smaller amount of hardware associated with the coarse tuning implementation. ...
... In the lowpass/highpass mode, the information in the quadrature-phase carrier is lost, because the output is only composed of in-phase carriers in those modes ( Table 1). The output frequency of the complex modulator ( @ ) should be higher than DC in those modes, so that the quadrature-phase data d k (n) is modulated to the in-phase carrier in (1). Furthermore, the frequency should be considerably higher than DC in the lowpass/highpass mode, so that the images generated by the analog upconversion could be filtered by the bandpass filter (BPF 2 in Fig. 1) (lowpass mode), and the images generated by the D/A conversion could be filtered by the analog reconstruction filter (BPF 1 in Fig. 1) (highpass mode). ...
The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f<sub>s</sub>/4, -f<sub>s</sub>/4,f<sub>s</sub>/2 (f<sub>s</sub> is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm<sup>2</sup> (0.35-μm CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).
... In conventional base station solutions, the carriers transmitted are combined after the power amplifiers. An alternative to this is to combine the carriers in the digital Intermediate Frequency (IF) domain [1] [2]. This saves a large number of analog components and because there is no analog I/Q modulator, many problems e.g. ...
In conventional base station solutions, the carriers transmitted are combined after the power amplifiers. An alternative to this is to combine the carriers in the digital domain. The major drawback of the digital carrier combining is a strongly varying envelope of the composite signal. The high PAR, sets strict requirements for the linearity of the power amplifier. High linearity requirements for the power amplifier leads to low power efficiency and therefore to high power consumption. In this paper, the possibility of reducing the PAR by clipping is investigated in two cases, GSM and EDGE.
In this research, we present the architecture and implementation of a Full-digital transmitter with radio frequency output targeting a System on Chip FPGA device. SoC FPGA devices have been widely adopted in the applications of digital signal processing (DSP) and digital communication. They are typically well suited for the evolving technology of software defined radios (SDR) due to their reconfigurability and programmability. However, SoC FPGA devices are mostly used to implement digital baseband and intermediate frequency (IF) functionalities. Therefore, significant analog and RF components are still needed to fulfill the radio communication requirements.
The Full-digital transmitter presented in this paper directly synthesizes RF signal in the digital domain, therefore eliminates the need for most of the analog and RF components. The Full-digital transmitter consists of one QAM modulator and one RF pulse width modulator (RF PWM). The binary output waveform from RF PWM is centered at 800MHz with 256-QAM signaling format. The entire transmitter is implemented using Altera Cyclone V SoC device with on chip Multi-Gigabit Transceiver (MGT). The adjacent channel leakage ratio (ACLR) measured in the 20 MHz passband is (-46dB). Our work extends the digital implementation of communication applications on a SoC FPGA platform to radio frequency, therefore making a significant evolution towards an ideal SDR.
Keywords: SDR system, Pulse Width Modulation, 256-QAM, Implementation via System on Chip FPGA.
