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Power Consumption in Clock Gated Frame Buffer

Power Consumption in Clock Gated Frame Buffer

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Figure 1: Schematic of Clock Gated Frame Buffer In Figure 1, there are...
Figure 2: Frame Buffer in Video Compression[1]
Table 2 : Power Consumption in Clock Gated Frame Buffer
Table 4 : Reduction of Power Consumption with Clock Gate on 10 GHz
+1 Table 5 : Reduction of Power Consumption with Clock Gate on 100GHz
Clock Gating Aware Energy Efficient Frame Buffer Design on FPGA
Conference Paper
Full-text available
  • Dec 2013
In this work, clock gating technique is applied on the Frame Buffers in order to get more energy efficient Frame Buffers. Frame Buffer is an in-built memory of digital Image Processor, which is writeable by the CPU and readable by the Video Interface and used to store color of each pixel. Clock gating is a power saving technique which turns off the...
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Context 1
... Table 1, clock power is 32mW, 315mW, 32mW, 315mW on 1GHz, 10GHz, 100GHz and 1THz device operating frequency respectively. From Table 2, we observe that Clock Gating technique is effective in reducing clock power (in range of 80-90% reduction of clock power) and less effective in order to reduce I/O power (10-30% reduction in I/O power) whereas it shows abnormal behavior for logic power and signal power. Power without Clock Gate Power with Clock Gate Clock Power 32mW 1mW Logic Power 1mW 1mW Signal Power 2mW 2mW I/Os Power 48mW 45mW When frame buffer is operating at 1GHz operating frequency, there is 96.88% reduction in clock power, 6.25% reduction in I/O power with clock gating. ...

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