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Port locations defined on the package. 1–5: ports for ground vias connected between C4s and g1 through g3. 6–9: ports for Vdd vias connected between C4s and v1 through v3. 1, 10–13: ports for ground vias connected between solder balls and g3. 14–17: ports for Vdd vias connected between solder balls and v3. 18, 19: ports for differential voltage measurement, ground on g1 and Vdd on v1.
Source publication
This paper presents simulation and analysis of core switching
noise for a CMOS ASIC test vehicle. The test vehicle consists of a
ceramic ball grid array (CBGA) package on a printed circuit board (PCB).
The entire test vehicle has been modeled by accounting for all the plane
resonances using the cavity resonator method. The models included both
the...
Contexts in source publication
Context 1
... CBGA package alone was modeled and simulated to un- derstand the effect of the package planes on core noise. The ports on the chip area of the package were defined as shown in Fig. ...
Context 2
... ports for ground and four ports for among 298 C4 pad locations were defined for the C4 locations on the package planes in the core area of the chip, as shown in Fig. 4. The same number of grounds and s were defined for the vias con- necting from the planes to the solder balls. The ground planes and planes were connected together using through vias at the C4 locations. The chip was powered at the bottom of the package by connecting an ideal voltage source to the solder ball locations between and ...
Context 3
... from the planes to the solder balls. The ground planes and planes were connected together using through vias at the C4 locations. The chip was powered at the bottom of the package by connecting an ideal voltage source to the solder ball locations between and ground. A current source as shown in Fig. 5 was connected between ports 5 and 9 in Fig. 4 to em- ulate the on-chip switching activity of one section of the chip, assuming that the power is supplied to that section through those ports where port 5 is a C4 node for ground and port 9 for . The fluctuation on the ASIC power supply was observed be- tween ports 18 and 19 in Fig. 4 where port 18 is a C4 node for ground and port 19 ...
Context 4
... as shown in Fig. 5 was connected between ports 5 and 9 in Fig. 4 to em- ulate the on-chip switching activity of one section of the chip, assuming that the power is supplied to that section through those ports where port 5 is a C4 node for ground and port 9 for . The fluctuation on the ASIC power supply was observed be- tween ports 18 and 19 in Fig. 4 where port 18 is a C4 node for ground and port 19 for , assuming the power is supplied to a quiet section of the chip through those ports. Vias, C4s and solder balls were modeled with lumped inductors of 15 pH, 10 pH, and 10 pH, respectively. The inductances for the C4s and solder balls were based on the number of these structures in ...
Citations
... Multilayer printed circuit boards (PCBs) or packages usually use entire layers or large area fills as ground reference planes or power distribution network (PDN) for integrated circuits (ICs) operating at a high speed [1]. While these power or ground planes provide ideal return paths for signal traces by constructing microstrip lines or striplines, they essentially form parallel plane waveguides in which high-speed via currents can easily excite propagating waves [2] [3]. This may cause strong coupling to adjacent vias, and thus leads to serious signal integrity (SI) problems. ...
A closed-form expression for via barrel-plate capacitances is derived. This results in a more accurate equivalent circuit model for decoupling capacitors including both parasitic inductances and via capacitances. Multilayer power distribution network (PDN) are then analyzed by incorporating the circuit models of both vias and parallel plane pair. Circuit simulator is used to evaluate the coupling properties among various locations in the multilayer PDN structures.
... under damped). Fig. 5 shows the spectrum of the measurement (obtained using a spectrum analyzer) and envelope estimates obtained using Equations (10) and (11) and the triangular waveform model. The pulse width is approximated as a half of the ringing period in the triangular model calculation, ∆t = π LC . ...
A resistance-inductance-capacitance (RLC) model is described for estimating current waveforms in digital CMOS circuits. The model is based on parameters that are readily derived from information available in board layout files and component data sheets or IBIS (I/O buffer information specification) files. Compared with the simpler triangular waveform traditionally used to approximate current in CMOS circuits, the RLC model more accurately estimates the shape of the current waveform in the time domain and the amplitudes of the upper harmonics in the frequency domain.
... A common method for suppressing resonant noise is to lower the ac impedance of the supply network by adding a large amount of decoupling capacitors (decaps) [4]. However, this approach has limitations such as the significant increase in gate leakage, which has already been reported to account for 15% to 20% of the total power in current microprocessors [5]. ...
Although there has been extensive research on controlling leakage power, the fact that leaky transistors can act as a damping element for supply noise has been long ignored or unnoticed in the design community. This paper investigates the leakage induced damping effect that helps suppress the supply noise. By developing physics-based impedance models for active and leakage currents, we show that leakage, particularly gate tunneling leakage, provides more damping than strong-inversion current. Simulations were performed in a 32nm CMOS technology to validate our models under PVT variations and to explore the voltage dependent behavior of this phenomenon. Design example utilizing leakage induced damping such as decap assignment is discussed with results showing 15.6% saving in decap area.
... A similar model has been used by other researchers to estimate both signal and power currents [4]- [18]. For example, N. Na used triangular waveforms to model core switching currents [8] [10]; L. Bouhouch used a similar waveform to model controller I/O switching currents [9]; and Kriplani employed a triangular waveform to model capacitive load currents [15]. The triangular waveform model has the advantage that it is based only on the amplitude and risetime of the voltage waveform. ...
A resistance-inductance-capacitance (RLC) model is described for estimating current waveforms in digital CMOS circuits. The model is based on parameters that are readily derived from information available in board layout files and component data sheets or IBIS files. Compared with the simpler triangular waveform traditionally used to approximate current in CMOS circuits, the RLC model more accurately estimates the shape of the current waveform in the time domain and the amplitudes of the upper harmonics in the frequency domain.
... Table III shows power supply noise simulation results for three 3-D placement schemes-no-decap aware, decap-aware, and decap-aware decap-placement. The P/G plane structure size is 246 mm 254 mm, and the top P/G plane pair was modeled using cavity resonator model [41] and simulated in HSPICE. The placement layer that uses this P/G plan includes 14 active devices. ...
Three-dimensional (3-D) packaging via system-on-package (SOP) is a viable alternative to system-on-chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this article, we present the first physical design algorithms for thermal and power supply noise-aware 3-D placement and crosstalk-aware 3-D global routing. Existing approaches consider the thermal distribution, power supply noise, and crosstalk issues as an afterthought, which may require an expensive cooling scheme, more decoupling capacitors (=decap), and additional routing layers. Our goal is to overcome this problem with our thermal/decap/crosstalk-aware 3-D layout automation tools. The traditional design objectives such as performance, area, wirelength, and via are considered simultaneously to ensure high quality results. The related experimental results demonstrate the effectiveness of our approaches
... A power/ground structure with thickness much less than the smallest wavelength of interest can be considered as a two-dimensional microwave planar circuit with n observable ports [7], and the associated Z-parameter matrix can be derived analytically using the cavity model for simple shapes. The cavity model of a rectangular power-bus structure developed for microstrip patch antennas [8], has been previously applied for power distribution networks in digital design as well [9,10,11]. ...
... Then, the power delivery network can be considered as a two-dimensional microwave planar circuit with n external observation ports. For power and ground planes with simple shapes, such as a rectangle and an equilateral triangle, the impedance matrix can be obtained analytically [7,9,10,11], as summarized in Table 1. ...
Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation.
... The non-slicing floorplanning algorithm can be classified into two approaches: mathematic programming based [85, 86], and heuristic based, such as simulated annealing[71, 72]. Simultaneous Switching Noise (SSN) [73] ...
... The trajectory optimization method works well with the circuits that have more correlation.Table 15 shows power supply noise simulation results for three 3D placement schemes: no-decap-aware, decap-aware, and decap-aware+decap-placement. The P/G plane structure size is 246 mm× 254 mm, and the top P/G plane pair was modeled using a cavity resonator model [73] and simulated in HSPICE. The placement layer that used this P/G plan includes fouteen active devices. ...
The focus of this research was to develop interconnect-centric physical design tools for 3D technologies. A new routing model for the SOP structure was developed which incorporated the 3D structure and formalized the resource structure that facilitated the development of the global routing tool. The challenge of this work was to intelligently convert the 3D SOP routing problem into a set of 2D problems which could be solved efficiently. On the lines of MCM, the global routing problem was divided into a number of phases namely, coarse pin distribution, net distribution, detailed pin distribution, topology generation, layer assignment, channel assignment and local routing. The novelty in this paradigm is due to the feed-through vias needed by the nets which traverse through multiple placement layers. To gain further improvements in performance, optical routing was proposed and a cost analysis study was done. The areas for the placement of waveguides were efficiently determined, which reduced delays and maximized utilization. The global router developed was integrated into a simulated-annealing based floorplanner to investigate trade-offs of various objectives. Since power-supply noise suppression is of paramount importance in SOP, a model was developed for the SOP power-supply network. Decap allocation, and insertion were also integrated into the framework. The challenges in this work were to integrate computationally intensive analysis tools with a floorplanning that works to its best efficency provided the evaluation of the cost functions are rapid. Trajectory-based approaches were used to sample representative data points for congestion analysis and interpolate the the congestion metric during the optimization schedule. Efficient algorithms were also proposed for 3D clock routing, which acheived equal skews under uniform and worst thermal profiles. Other objectives such as wirelength, through-vias, and power were also handled. Gabriel H. Loh, Committee Member ; Gabriel Rincon-Mora, Committee Member ; Madhavan Swaminathan, Committee Member ; Abhijit Chatterjee, Committee Member ; Sung-Kyu Lim, Committee Chair. Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
... The peaks in both and correspond to the power-bus resonances. The first few distinguishable TM modes are identified in Fig. 4. Employing a cavity model, all matrix elements in (7) can be calculated analytically for a rectangular parallel-plate area fill or power-bus as [17]- [20], (11) with , , , the dielectric loss factor given by , the skin depth given by , and the angular resonance frequencies for mode indexes and . The plane dimensions in the and directions are denoted as and , respectively, and is the separation between the planes. ...
... Consider a single-ended trace with a via transition located at Port 0 (the center between two differential vias), as shown in Fig. 8. The power-bus noise voltage due to the trace current flowing through a via transition is (19) Assuming equal currents , the differential-to-single ratio of noise voltages can be defined as (20) In the above definition, was replaced by , according to the approximation (15). The upper limit of is then (21) An evaluation of (21) is shown in Fig. 12 based on the same board geometry used to evaluate (18). ...
Differential and common-mode transfer impedances are proposed herein to analyze noise coupled to (from) the dc power-bus from (to) via transitions in differential signals. Expressions for the two transfer impedances in terms of conventional single-ended transfer impedances are derived and verified through measurements, full-wave finite-difference time-domain (FDTD) simulations and an analytical cavity model. Some properties of the differential and common-mode transfer impedances are investigated to facilitate engineering design. The impact of signal current imbalances on power-bus noise and the benefit of differential signals as compared to single-ended signals are quantified.
... We report SSN noise for each block placed in the top placement layer. The P/G plane structure size is 246mm× 254mm, and the top P/G plane pair was modelled using cavity resonator model [19] and simulated in HSPICE. The placement layer that uses this P/G plan includes 14 active devices. ...
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this work, we propose a 3D module and decap (decoupling capacitance) placement algorithm that simultaneously reduces the power supply noise and wire congestion. We provide efficient algorithms for 3D power supply noise and congestion analysis to guide our 3D module placement process. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both decap amount and congestion with only small increase in area, wirelength, and runtime.
... In the past, various methods have been formulated to model and analyze the passive part of the power distribution network [which gives the frequency domain representation of the power distribution system (PDS)]. Examples include the transmission line method [3], [4], which uses a two-dimensional array of transmission lines or distributed lumped elements in SPICE, the cavity resonator method [5], [6], and the transmission matrix method [7]- [9]. Equally important in the analysis of SSN is the extraction of the switching noise current that is injected into the PDS at every clock cycle. ...
This paper discusses a measurement-based approach for estimating the switching noise current waveform in a functioning computer system. The proposed method consists of a wavelet-based approach for denoising the measured waveform and a technique for capturing the result in an accurate and compact model. The method has been tested on simulated and measured data. The test case considered is a high-speed functioning workstation from Sun Microsystems. Using the current source developed, simultaneous switching noise in the power distribution network of the test system has been simulated with good accuracy
