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We report the design and characterisation of a 32times32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130 nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50 mum pitch TDC array exhibits a minimum time resolution of 50 ps, with accuracy of plusmn0.5 LSB DNL and 2.4...
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... report the design and characterisation of a 32x32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50 μ m pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats. The origins of modern time to digital conversion are rooted in nuclear science and aerospace activities of the 1960’s [1] and today may be broadly classified into two groups: those whose time resolution is based on the minimum gate delay available in the process technology, and those achieving sub-gate delay resolution. The gate delay limit may be bettered by using Vernier delay lines (VDLs) [2], pulse shrinking [3] or by interpolative means [4]. Other members of this group implement time stretching [5] and time to amplitude converter (TAC) [6] approaches. TDC’s based on the minimum gate delay are classically based on clocked delay lines as presented in the hybrid approach of [7] which also utilises a single ended ring oscillator. Converters based on the ring oscillator approach [8,9] also belong to this group and is the chosen approach for this work based on their suitability for array implementation. The recent progress of implementation of SPADs in nanometer scale CMOS now makes it possible to integrate detector and converter functions on chip to create a monolithic TCSPC system. This work constitutes the largest single-chip array of TDCs so far reported. A new TDC architecture combining small area, low power consumption and scalability at moderate resolution (50ps) is discussed. As opposed to a stand-alone single TDC design, an arrayable architecture is a trade off between time resolution, word width, complexity, area, power consumption and accuracy. This is particularly evident when considering a structure that scales elegantly to large format arrays. Using ST Microelectronics’ 130nm, 4 metal CMOS Imaging process and 1.2V digital core, we employ a combined coarse-fine architecture. Coarse conversion is achieved by incrementing a ripple counter on every ring period, with fine conversion being decoded from the ‘frozen’ dynamic state of the internal nodes of the ring. The logic block generates ring oscillator differential control signals using only high-speed combinatorial logic to avoid flip-flop setup and hold violations. The block diagram of the TDC is shown in Fig.1. The TDC is embedded with buffer memory, glue logic and SPAD to create a 50 μ m x 50 μ m time correlated imaging pixel shown in Fig. 2. Dynamic range can be doubled in an area efficient manner by adding one extra counter flip flop and pipeline memory element. The pixel design supports pipelined data readout and may be instantiated many times to create any desired ...
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Citations
... Multiple architectures exist for the in-pixel timestamping of circuits in time-resolved, single-photon image sensors, including analog [28] and digital [29,30] implementations. The latter ones are typically based on ring oscillators and can be divided into two main groups: one based on a global ring, whose phases are distributed across the entire array [31,32], and one with replicas of a ring oscillator in every pixel [33]. With a local ring, power consumption is optimized thanks to the reversed start-stop operation. ...
Single-photon detection and timing has attracted increasing interest in recent years due to their necessity in the field of quantum sensing and the advantages of single-quanta detection in the field of low-level light imaging. While simple bucket detectors are mature enough for commercial applications, more complex imaging detectors are still a field of research comprising mostly prototype-level detectors. A major problem in these detectors is the implementation of in-pixel timing circuitry, especially for two-dimensional imagers. One of the most promising approaches is the use of voltage-controlled ring resonators in every pixel. Each of these runs independently based on a voltage supplied by a global reference. However, this yields the problem that the supply voltage can change across the chip which, in turn, changes the period of the ring resonator. Due to additional parasitic effects, this problem can worsen with increasing measurement time, leading to drift in the timing information. We present here a method to identify and correct such temporal drifts in single-photon detectors based on asynchronous quantum ghost imaging. We also show the effect of this correction on recent quantum ghost imaging (QGI) measurement from our group.
... In the past few years, imaging devices with single-photon sensitivity and high temporal resolution have emerged. Using those imaging devices, such as streak cameras [9], photonic mixer devices (PMD) [10], and single-photon avalanche diode (SPAD) cameras [11], 3D LiF imaging of light traveling through static scenes, propagating in optical fibers [12], and being reflected by mirrors [13] was achieved by detecting the scattered photons from the flying light. ...
... Thus, only limited or partial programmability is possible. Examples include different histogram binning and on-chip data compression levels, often obtained by employing some degree of circuit sharing to minimize silicon real estate [8,10,11,16,[18][19][20][21][22]. Programmability by means of digital processing units combined to a backside-illuminated SPAD array has been reported in [12], in-pixel reconfigurable logic in [23], and modular photon processors in [9,24], allowing to switch between intensity and time-resolved operating modes. ...
We report on LinoSPAD2, a single-photon camera system, comprising a 512×1 single-photon avalanche diode (SPAD) front-end and one or two FPGA-based back-ends. Digital signals generated by the SPADs are processed by the FPGA in real time, whereas the FPGA offers full reconfigurability at a very high level of granularity both in time and space domains. The LinoSPAD2 camera system can process 512 SPADs simultaneously through 256 channels, duplicated on each FPGA-based back-end, with a bank of 64 time-to-digital converters (TDCs) operating at 133 MSa/s, whereas each TDC has a time resolution of 20 ps (LSB). To the best of our knowledge, LinoSPAD2 is the first fully reconfigurable SPAD camera system of large format. The SPAD front-end features a pitch of 26.2 μm, a native fill factor of 25.1%, and a microlens array achieving 2.3× concentration factor. At room temperature, the median dark count rate (DCR) is 80 cps at 7 V excess bias, the peak photon detection probability (PDP) is 53% at 520 nm wavelength, and the single-photon timing resolution (SPTR) is 50 ps FWHM. The instrument response function (IRF) is around 100 ps FWHM at system level. The LinoSPAD2 camera system is suitable for numerous applications, including LiDAR imaging, heralded spectroscopy, compressive Raman sensing, and other computational imaging techniques.
... This provides single-photon sensitivity and picosecond resolution for time-offlight measurements [4,[7][8][9]. In the array type single-photon counting LiDAR [10][11][12], each avalanche photodiode detector is integrated with a TCSPC module [13][14][15], which greatly reduces the 3D imaging time [7,16,17] and enables long-range depth imaging [12]. However, the circuitry occupies a significant portion of the space surrounding SPAD chip, resulting in very low proportion of the avalanche multiplication area and thus a low native resolution [13,18,19]. ...
Currently, mainstream light detection and ranging (LiDAR) systems usually involve a mechanical scanner component, which enables large-scale, high-resolution and multi-spectral imaging, but is difficult to assemble and has a larger system size. Furthermore, the mechanical wear on the moving parts of the scanner reduces its usage lifetime. Here, we propose a high-resolution scan-less multi-spectral three-dimensional (3D) imaging system, which improves the resolution with a four-times increase in the pixel number and can achieve multi-spectral imaging in a single snapshot. This system utilizes a specially designed multiple field-of-view (multi-FOV) system to separate four-wavelength echoes carrying depth and spectral reflectance information with predetermined temporal intervals, such that one single pixel of the SPAD array can sample four adjacent positions through the four channels’ FOVs with subpixel offset. The positions and reflectivity are thus mapped to wavelengths in different time-bins. Our results show that the system can achieve high-resolution multi-spectral 3D imaging in a single exposure without scanning component. This scheme is the first to realize scan-less single-exposure high-resolution and multi-spectral imaging with a SPAD array sensor.
... More recently, single-photon avalanche diode (SPAD) arrays have reached a high technological maturity [21,22], featuring observation rates up to 1 MHz, a fill-factor close-to 100%, and megapixel spatial resolution [23]. Furthermore, different functionalities such as a time-to-digital converter (TDC) with ∼50 ps temporal resolution [24] and in-pixel memories can be integrated in-chip performing various detection operations, such as timestamping, counting, and gating. Such achievements have brought about tremendous state-of-the-art advancements in a number of bio-and quantum-imaging applications, including near-infrared (NIR) fluorescence lifetime imaging [25], pixel super resolution [26], quantum optical centroid measurements [27], EPR inequality characterization [28], correlation plenoptic imaging [29], Hong-Ou-Mandel interference microscopy [30], and ranging [31]. ...
Quantum ghost imaging (QGI) is an intriguing imaging protocol that exploits photon-pair correlations stemming from spontaneous parametric down-conversion (SPDC). QGI retrieves images from two-path joint measurements, where single-path detection does not allow us to reconstruct the target image. Here we report on a QGI implementation exploiting a two-dimensional (2D) single-photon avalanche diode (SPAD) array detector for the spatially resolving path. Moreover, the employment of non-degenerate SPDC allows us to investigate samples at infrared wavelengths without the need for short-wave infrared (SWIR) cameras, while the spatial detection can be still performed in the visible region, where the more advanced silicon-based technology can be exploited. Our findings advance QGI schemes towards practical applications.
... As a result, the CMOS-based SPAD sensor solutions are being applied to various applications requiring time-resolved imaging, such as light detection and ranging (LiDAR) to control and navigate autonomous vehicles [3]- [6], airborne laser mine detection system (ALMDS) to identify a target in military applications [7], service drones [8], machine vision [9], security, and biomedical imaging including fluorescence lifetime imaging (FLIM) [10], positron emission tomography (PET) [11], and near-infrared optical tomography (NIROT) that can diagnose the human brain and body [12]. One challenge of the CMOS-based approach is that the on-chip electronics occupy a considerable area and it becomes more severe as more functionalities like counting, timestamping, processing, and compression are required, which results in a small area to implement the SPAD, i.e., low fill factor (FF) [13], [14]. Such a trade-off not only limits the spatial resolution of a SPAD sensor but also increases the chip size and cost. ...
This article introduces a back-illuminated (BI) single-photon avalanche diode (SPAD) based on 40 nm CMOS image sensor (CIS) technology which is the most advanced technology node for the fabrication of a SPAD up to date. It's based on a P-well (PW) and deep N-well (DNW) junction, and the DNW is deeply implanted to form a wide absorption region resulting in very high and wide photon detection probability (PDP). Thanks to the retrograde DNW, the premature edge breakdown phenomenon is completely prevented and the whole area of the planar junction becomes a high-efficient avalanche multiplication region. In addition, an anti-reflection coating on the backside of the SPAD and a metal reflector at the bottom reduce the reflection of incoming photons and improve the efficiency at long wavelengths, respectively. With the most advanced CIS technology for BI SPADs, the presented SPAD accomplishes a dark count rate (DCR) of 70 cps/μm
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, peak PDP of 81% at 675 nm, and PDP of 39% at 940 nm. The timing jitter is 79 ps full width at half-maximum width (FWHM), which is the best timing jitter performance among BI SPADs reported so far. All the values are obtained with the excess bias voltage of 6 V.
... In this paper we focus on Light Detection And Ranging (LiDAR) / direct-Time-of-Flight (d-ToF) measurement based on Single-Photon Avalanche Diodes (SPAD), which is one of the most promising among active techniques [4], [5]. In a SPAD-based d-ToF measurement, the distance is extracted by measuring the traveling time of a pulse of light projected from the source and reflected back by the target to a detector that consists of a SPAD operating as a photon-to-edge converter, coupled to a photon timestamping circuit (usually a Time-to-Digital Converter (TDC) or a Time-to-Amplitude Converter (TAC)) [6]- [8]. Due to hardware limitations, such as the detector dead-time and the statistical nature of photons, together with the presence of uncorrelated background light, a number of observations are usually accumulated into a histogram memory to enhance the signal to noise ratio and extract the target distance by means of signal processing techniques [9]- [11]. ...
We present a new method to acquire the 3D information from a SPAD-based direct-Time-of-Flight (d-ToF) imaging system which does not require the construction of a histogram of timestamps and can withstand high flux operation regime. The proposed acquisition scheme emulates the behavior of a SPAD detector with no distortion due to dead time, and extracts the
TOF
information by a simple average operation on the photon timestamps ensuring ease of integration in a dedicated sensor and scalability to large arrays. The method is validated through a comprehensive mathematical analysis, whose predictions are in agreement with a numerical Monte Carlo model of the problem. Finally, we show the validity of the predictions in a real d-ToF measurement setup under challenging background conditions well beyond the typical pile-up limit of 5% detection rate up to a distance of 3.8 m.
... Slave gated VCRO-based TDC belongs to this type. A control voltage from the PLL is distributed to each in-pixel VCRO to set the desired oscillation frequency [9]. The power consumption of this voltage distribution network is negligible. ...
... The recently published gated VCRO based TDCs for large array imagers start oscillating from a fixed state controlled by a rest or initialization signal [9], [11], [19], [21]. The benefit of doing so is that the initial state corresponds to 0 (generated by the encoder), so the encoder result after the STOP instant refers directly to the actual quantized code. ...
... Otherwise, the error will be accumulated and result in large quantization error for long range detection applications. A PLL with programmable divider can be used to overcome the global drift and stabilize the oscillation frequency [9], [23], [30]. The PLL used in this work is shown in Fig. 15, which includes a phase frequency detector (PFD), a charge pump (CP), a source follower (SF), a replica VCRO, a programmable divider, and an external lead-lag loop filter. ...
This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18- $\mu$ m HV-CMOS technology in a 32 $\times$ 32 array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.
... The 64 × 64 by Schwartz [37] in 2007 features one TDC every SPAD with 350 ps coarse time resolution, plus a multiphase clock interpolator in a 350 nm HVCMOS technology. The 32 × 32 by Richardson [38] in 130 CIS technology achieve 50 ps resolution and 1 Mfps readout. More general architectures have been proposed, with both timing and counting electronics to achieve great versatility in the final application (e.g., Villa [39] and Manuzzato [40]). ...
The ability to detect single photons is becoming an enabling key capability in an increasing number of fields. Indeed, its scope is not limited to applications that specifically rely on single photons, such as quantum imaging, but extends to applications where a low signal is overwhelmed by background light, such as laser ranging, or in which faint excitation light is required not to damage the sample or harm the patient. In the last decades, SPADs gained popularity with respect to other single-photon detectors thanks to their small size, possibility to be integrated in complementary metal-oxide semiconductor processes, room temperature operability, low power supply and, above all, the possibility to be fast gated (to time filter the incoming signal) and to precisely timestamp the detected photons. The development of large digital arrays that integrates the detectors and circuits has allowed the implementation of complex functionality on-chip, tailoring the detectors to suit the need of specific applications. This review proposes a complete overview of silicon SPADs characteristics and applications. In the previous Part I, starting with the working principle, simulation models and required frontend, the paper moves to the most common parameters adopted in literature for characterizing SPAD performance and describes single pixels applications and their performance. In this Part II, the focus is posed on the development of SPAD arrays, presenting some of the most notable examples found in literature. The actual exploitation of these designs in real applications (e.g., automotive, bioimaging and radiation detectors) is then discussed.
... SPAD sensors can be integrated and manufactured inexpensively in standardized semiconductor manufacturing processes with a wide range of pixel array sizes, from single pixel detectors to megapixel SPAD arrays. [1][2][3][4][5][6] Often, sensors and readout circuits are fabricated side-by-side on the same chip, representing a high degree of integration and resulting in short signal propagation times. Pixel fill-factors can be improved through the use of three-dimensional (3D)-stacking and microlens arrays. ...
... For an event read-out with forwardsampling, the event time t i equals simply the the bin number (b i ) times the sampling bin width (Δt bin ), see Eq. (2). In the case of reverse sampling, first, we have to convert the bin number by subtraction from the total number of bins N bins , as given in Eq. (2). ...
