Pipelined memory access: reading, processing and writing each column in 3 consecutive clock cycles increases overall processing throughput. 

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... 7: Combinational logic for next state computation. To compute the next state for a column of cells three separate operations need to be performed. A memory read operation, next state computation and a memory write operation. Because next state computation requires fairly simple logic, memory read and write operations are relatively long in comparison. It is possible to pipeline these three operations to increase the overall throughput, as shown in figure 8. If the next computation logic was quite complex, it could be beneficial to also pipeline it by dividing it up into smaller computation stages; however, in this case it would not achieve any gains. We used Verilog HDL to describe the design. Verilog description of the processing element is shown in algorithm 1. It consists of two parts: first part is the always statement that describes a synchronous three-element shift register using three non-blocking assignment <= opera- tors. These assignments are executed simultaneously in a single clock cycle, using the value of each variable on the right hand side from the previous clock cycle. The value of this shift register is assigned to the reg out port to be passed to PE above and PE below. The second part consists of computation of the number of alive neighbors by summing their states and the computation of the next state by applying the game rules. This code, along with  ...