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Most of the research in the field of nanoelectronics has been focused on nanodevice and nano-fabrication aspects. By contrast, very little work has been reported on the design or ca-pabilities of circuits and computational architectures that can be built out of nanodevices. A key challenge in any nanoscale system is to preserve the density advantag...
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... A variety of such schemes are introduced and evaluated. Simulations performed on the Wire Streaming Processor 0 (WISP-0) [35], built on the NASIC computational fabric demonstrate a 23% improvement in the effective yield (yield per unit area) for FastTrack schemes along with 79% lower degradation in mean operating frequency compared to conventional techniques at 10% defect rate. FastTrack schemes perform well across both the effective yield and performance metrics, and show an improvement of 122% -268% in effective yield-performance products at defect rates of 8% -12% compared to conventional schemes performing best at the same defect rates. ...
... Fig. 1 shows a single NASIC tile (consisting of 2 dynamic NAND stages) implementing a 1-bit full adder. Many such tiles can be cascaded together to build a large-scale system such as a processor [35] or an image processing architecture [36]. ...
... Each nanotile is surrounded by microwires that carry ground, power supply voltage, and some control signals needed for dynamic data streaming. A block diagram of the WISP-0 nanoprocessor Fig. 7. Details of the WISP-0 can be found in [29][30] [35]. ...
High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly-based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuits and logic styles. Development of analytical fault models for nanosystems is necessary to explore the design of novel fault tolerance schemes that could be more effective than conventional schemes. In this paper, we first develop a detailed analytical fault model for the nanoscale application specific integrated circuits (NASIC) computing fabric and show that the probability of 0-to-1 faults is much higher than of 1-to-0 faults. We then show that in fabrics with unequal fault probabilities, using biased voting schemes, as opposed to conventional majority voting, could provide better yield. However, due to the high defect rates, voting will need to be combined with more fine-grained structural redundancy for acceptable yield. This entails degradation in performance (operating frequency) due to an increase in circuit fan-in and fan-out. We, therefore, introduce a new class of redundancy schemes called FastTrack that combine nonuniform structural redundancy with uniquely biased nanoscale voters to achieve greater yield without a commensurate loss in performance. A variety of such techniques are employed on a wire streaming processor (WISP-0) implemented on the NASIC fabric. We show that FastTrack schemes can provide 23% higher effective yield than conventional redundancy schemes even at 10% defect rates along with 79% lesser performance degradation.
... The output of horizontal nanowires acts as n+ gate to the next set of transistors whose channels are aligned in the vertical direction (right NAND plane). Multiple such NASIC tiles are cascaded together to form more complex circuitry such as microprocessors [14] and image processing systems [15]. Fig. 2(a) shows one possible enhancement-mode xnwFET structure integrated into NASICs. ...
Junctionless field-effect transistors (FETs) are promising emerging devices with simple doping profiles. In these devices, the channel is uniformly doped without the need for extremely good lateral doping abruptness or high thermal budget at source/channel and drain/channel junctions. This implies that device customization requirements are simplified compared to conventional enhancement-mode FETs. However, junctionless FETs have been discussed exclusively in the context of MOSFET replacement assuming other CMOS manufacturing, circuit and interconnect paradigms to be preserved intact. In this paper we argue for integration of junctionless devices into emerging nanofabrics. We propose junctionless crossed-nanowire FETs (xnwFETs) as the active devices for the Nanoscale Application Specific Integrated Circuits (NASICs) crossed nanowire fabric. We show that in addition to reducing customization requirements for individual nanodevices, the simpler device doping profile enables a scalable manufacturing pathway for NASICs where alignment and overlay requirements are minimized. In this pathway, a uniform 2-D nanowire grid may be assembled using unconventional or self-assembly based approaches without any overlay constraints. Overlay requirements exist only for subsequent photolithography steps, which is expected to be very precise (3σ = ±3.3nm for 16nm technology node).
... We present a 3-D nanofabric called N 3 ASICs, that can be built using the proposed approach and evaluate its benefits against 16nm CMOS technology. A nanoprocessor (WISP-0 [5]) is mapped to this fabric for the purpose of study. Results show that a yield of 100% is obtained even for an overlay imprecision of 8nm (based on manufacturing solutions known according to ITRS 2009) with a density advantage of 3X. ...
Several nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. However, their integration and interfacing with external CMOS has received only limited attention. In this paper we explore integration challenges for nanoscale fabrics focusing on registration and overlay requirements especially. We address the following questions: (i) How can we mitigate the overlay requirements between nano-manufacturing and conventional lithography steps? (ii) How much overlay precision is necessary between process steps? and (iii) What is the impact on yield if different overlays are used? We propose and evaluate a new D integration approach that combines standard CMOS design rules with nano-manufacturing constraints. For a nanoprocessor design implemented in N3ASIC (a hybrid nanowire-CMOS fabric) we show that a 100% yield is achievable even for overlay precisions achievable with current CMOS manufacturing (3σ=±8nm, ITRS 2009) while still retaining 3X density advantage compared to a projected 16nm CMOS scaled design.
... The output of horizontal nanowires acts as gate to the next set of transistors whose channels are aligned in the vertical direction (right NAND plane). Multiple such NASIC tiles are cascaded together to form more complex circuitry such as microprocessors [10] and image processing systems [11]. ...
This fabric update summarizes recent advances for the Nanoscale Application Specific Integrated Circuits (NASICs) nanoscale computing fabric. We provide a brief overview of NASICs, and discuss recent work at all fabric levels. We present advances in device design and optimization including omega gated and junctionless nanowire field effect transistors, methodologies for validation of functionality and parameter variation evaluation, new circuit-level sequencing schemes and performance optimization techniques. We also discuss techniques for defect and parameter variation resilience, ongoing fabrication directions including prototyping and scalable assembly efforts, and directions for the future.
... Given the technological and financial limitations, there are increasing incentives to explore new avenues to implement the required function. While some of the directions look at new types of devices (such as cross-nanowire transistors [1], [2], [3]), others explore novel physical phenomena (using electron spin [4] instead of charge) and alternative materials such as carbon, to build electronic devices and circuits. ...
Graphene exhibits extraordinary electrical properties and is therefore often envisioned to be the candidate material for post-silicon era as Silicon technology approaches fundamental scaling limits. Various Graphene based electronic devices and interconnects have been proposed in the past. In this paper, we explore the possibility of a hybrid fabric between CMOS and Graphene by implementing a novel Graphene Nanoribbon crossbar (xGNR) based volatile Tunneling RAM (GNT RAM) and integrating it with the 3D CMOS stack and layout. Detailed evaluation of GNT RAM circuits proposed show that they have considerable advantages in terms of power, area and write performance over 16nm CMOS SRAM. This work opens up other possibilities including multi-state memory fabrics and even an all-graphene fabric can be envisioned on the long term.
... Built-in defect tolerance schemes provide resilience against manufacturing defects such as stuck-on xnwFETs. The NASIC WIre Streaming Processor version-0 (WISP-0) [15], [16] is a stream processor on the NASIC fabric that is used as a test case for quantifying variability (specifically performance degradation). The main contributions of this paper are: i) A novel methodology for integrated exploration of parameter variability across nanodevice, circuit and system levels is presented; and ii) Variability effects are analyzed in detail for xnwFET devices and associated NASIC circuits and systems.Figure 1. Methodology integrating device, circuit and architectural level explorations ...
... Clustered defects may also be handled. Additional information on defect tolerance and models can be found in [5], [6], [15]. For parameter variations, timing characterizations of NAND gates from HSPICE are used. ...
... Architectural simulations of the NASIC WISP-0 processor [15], [16] were carried out using the architectural simulation framework described inFig. 1 and Section II-C. Gate delay distributions obtained from Monte Carlo simulations of NASIC dynamic NAND gates were sampled for each gate in the design and the maximum operating frequency at which the processor functioned without missed deadlines was estimated. ...
Emerging nano-device based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this paper, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated framework enables to study in detail the impact of physical parameter variation across all fabric layers for the first time. The framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 40% deviation from nominal. Monte Carlo simulations using the architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. However, given high defect rates in nano-manufacturing, built-in fault tolerance needs to be incorporated for achieving acceptable yields. These techniques are shown to also ameliorate the effects of parameter variation.
... We use the wire streaming processor (WISP)-0 [13] design to evaluate the benefits of the modified NASIC fabric with the new logic family. For the purpose of the evaluation, WISP-0 is implemented on both the AND–OR and the AND–OR/NOR fabrics as well as in CMOS. ...
... Fig. 2 shows a waveform that illustrates the discharge–evaluate–hold phases for AND circuits . Details on dynamic circuits and their applications in NA- SICs can be found in [10] and [13]. To validate the concept of dynamic circuits and analyze the sensitivity of circuits to key device parameters, we evaluate the signal integration issue of cascaded dynamic circuits using circuit-level simulations in [23]. ...
... In the circuit in Fig. 3, we generate negative outputs ∼c 1 and ∼s 0 for cascading in multitile designs . Refer to [7], [8], [10], [11], and [13] for more details. NASICs can use a single type of FET, as shown in [14]: this simplifies manufacturing and improves overall performance. ...
Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g., AND-OR, NOR-NOR, NAND-NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it. We find that it also improves the efficiency of fault tolerance techniques as it significantly simplifies the designs. In addition, we found that it enables voting at nanoscale that can improve fault tolerance further. A nanoscale processor is implemented for evaluation purposes. We found that compared with an implementation on a Nanoscale Application-Specific IC (NASIC) fabric with one type of two-level logic, the density of this processor improves by up to 52% by using the heterogeneous logic. Furthermore, the yield is improved by 15% at 2% defective transistors and by 147% at 5% defect rates. Detailed analysis on density and yield is provided. The approach is applicable in grid-based fabrics in general, e.g., it can be used in both NASIC and hybrid semiconductor/nanowire/molecular (CMOL) designs.
... Weng et al. propose a nanoarchitecture that can be configured into an application domain known as NASIC [12], [24], [25]. Generally, NASIC is modification of the nanoPLA. ...
... In order to compared the difference in required area between CMOS and NASIC, an experiments is performed. Durint experiment, a wire streaming processor is designed on 30nm [24] and 18nm [25] CMOS was compared withe same circuit desigened using NASIC. Synthesization results each shows that CMOS occupies around 15× and 12× larger than NASIC, respectively. ...
This tutorial paper discusses and analyzes different hybrid nanoarchitectures that are structured using crossbar arrays. Such nanoarchitectures are likely to be used for building future computing systems. The hybrid CMOS/nanodevice architectures leverage the advantage of CMOS maturity and potentials in nanodevice (e.g. high density, low power consumption, reduced manufacturing costs, new functionality, etc.), to aid their mission in increasing the performance better than current CMOS-based architectures. We first describe the concept of crossbar-based nanoarchitecture and then classify the nanoarchitectures into two distinct structures; two-dimensional structures and three-dimensional structures. Subsequently, a detail analysis of each structure is presented including e.g., advantages in terms of area and performance over CMOS-based circuits. Finally, the most promising crossbar-based hybrid nanoarchitecture is suggested.
... The models described above are illustrated through some emerging nanoscale fabrics in table I. Special focus is given on NASIC fabric for deeper explanations as case study. NASIC [19][20][21] is a hybrid system based around tiles of nanowires and FETs with CMOS providing support and some control circuitry. The tiles are made up of crossed nanowires with FETs at the intersections, forming cascaded PLA-like structures. ...
... WISP-0[20] is a stream processor, built on NASIC, that implements a streaming processor architecture with 5-stage pipeline: fetch, decode, register file, execute, and write back. It is a multi-tile design with 5 nanotiles. ...
The design of CAD tools for nanofabrics involves new challenges not encountered with conventional CMOS technology. In this paper, we describe the design of a prototyping CAD tool targeting design automation of applications on a wide range of nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between the fabrics. This tool supports the design flow from behavioral description to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.
... Arrows show propagation of data through the tile. Fig. 2 demonstrates the design of a simple 1-bit NASIC full adder in dynamic AND-OR style [7]. The thinner wires represent NWs. ...
... In NASICs, this hold phase also provides temporary storage of output values on NWs. Details regarding this aspect could be found in [6] [7]. ...
... By using dynamic circuits and pipelining on the wires, NASICs eliminate the need for explicit flip-flops in many areas of the design [6] and achieve unique pipelining schemes. Fig . 2 demonstrates the design of a simple 1-bit NASIC full adder in dynamic AND-OR style [7]. The thinner wires represent NWs. ...
The rapid progress of manufacturing nanoscale devices is pushing researchers to explore appropriate nanoscale computing architectures for high density beyond the physical limitations of conventional lithography. However, manufacturing and layout constraints, as well as high defect/fault rates expected in nanoscale fabrics, could make most device density lost when integrated into computing systems. Therefore, a nanoscale architecture that can deal with those constraints and tolerate defects/faults at expected rates, while still retaining the density advantage, is highly desirable. In this paper, we describe a novel nanoscale architecture based on semiconductor nanowires: NASICs (nanoscale application specific ICs). NASIC is a tile-based fabric built on 2-D nanowire grids and NW FETs. WISP-0 (wire streaming processor) is a processor design built on NASIC fabric where NASIC design principles and optimizations are applied. Built-in fault tolerance techniques are applied on NASICs designs to tolerate defects/faults on-the-fly. Evaluations show that compared with the equivalent CMOS design with 18 nm process (the most advanced technology expected in 2018), WISP-0 with combined built-in redundancy could be still 2~3X denser. Its yield would be 98% if the defect rate of transistors is 5%, and 77% for 10% defective transistors.
