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A novel class of filters (called pipe filters) that features in-band noise reduction is presented and a current mode biquad cell based on cross-connected cascoded devices is introduced. The presented solution gives in-band high-pass noise shaping and passive pre-filtering of out-of-band blockers. This results in both low in-band noise and high out-...
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Context 1
... filter is to consider it as a "pipeline" in which current is flowing and where a signal attenuation (frequency dependent) corresponds to a current loss through a leakage. Under this model, in the passband, the filter works as a lossless pipe where the input cur- rent is equal to the output one and thus no noise or distortion can be added to it [ Fig. 2(a)]. On the contrary, in the stop band, the current leakage allows both noise and distortion component to enter the pipe and reach the output. This occurs for example for the noise produced by the transistor when the capacitor is no more an open circuit [ Fig. 2(b)]. In general, any kind of opera- tion performed on the current that flows ...
Context 2
... rent is equal to the output one and thus no noise or distortion can be added to it [ Fig. 2(a)]. On the contrary, in the stop band, the current leakage allows both noise and distortion component to enter the pipe and reach the output. This occurs for example for the noise produced by the transistor when the capacitor is no more an open circuit [ Fig. 2(b)]. In general, any kind of opera- tion performed on the current that flows in the pipe can perturb the signal and introduce noise. An example is signal amplifica- tion that is obtained by injecting in the pipe an extra current pro- portional to the input current. For this reason, to ensure (at least ideally) that no noise is introduced ...
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Citations
... But traditional Gm-C filters suffer from poor noise and linearity issues. To improve their performances, several current mode filters were reported in [22,23,24,25,26,27,28,29]. Among them, [25] introduces a high linearity current mode noise shaping filter, but its bandwidth is only 2.8 MHz, which is not feasible for high speed applications. ...
... To improve their performances, several current mode filters were reported in [22,23,24,25,26,27,28,29]. Among them, [25] introduces a high linearity current mode noise shaping filter, but its bandwidth is only 2.8 MHz, which is not feasible for high speed applications. The current mode TIA based filter presented in [26] has a bandwidth of 1 GHz, but suffers from a very limited IIP3. ...
... It provides a transformation from the voltage to the current domain. The main principle of a current mode Gm-C filter is to remove the voltage to current transformation cell at the input of a traditional Gm-C filter [25]. As shown in Fig. 1, a 2 nd order current mode Gm-C filter is actually a RLC network. ...
This paper presents a complementary current-mode 2nd order Gm-C filter for 5G and other broadband applications. The filter structure is based on 2 complementary differential pairs in order to achieve both low noise and high frequency performances. A bandwidth of higher than 1GHz is achieved with a gain of 0dB and an in-band IIP3 of 29dBm, consuming less than 27mW from a 1.8V supply. The filter is fabricated in a 65nm CMOS process with a core circuit area of 0.1mm × 0.08mm.
... For measurements, a voltage source is fed into the filter through large external resistors (R ext ) in series, similar to what has been done in [20]. The voltage source together with R ext models the Thévenin equivalent of a g m -cell with a finite output resistance (Fig. 12). ...
A third-order passive switched-capacitor low-pass filter is presented together with experimental results. The current input-voltage output filter structure realizes complex-conjugate poles although it is composed of switches and capacitors. The results are verified with measurements performed on the filter prototype integrated in a 0.13 = μm CMOS technology. The prototype has a cut-off frequency of 470 kHz, 150-μW power consumption from 1.2-V power supply, 92-dB SFDR, and an active area of 0.06 mm². The switch-capacitor filter was obtained using a continuous-time model that is also described here and is useful for design, analysis, and simulation of oversampled switched-capacitor circuits. The model is applicable to a variety of topologies including multi-phase passive switched-capacitor filters, switched-capacitor integrators, as well as switched-capacitor dc/dc converters.
... Then, down-converted interferers are further suppressed by the proposed TIA with a fourth-order low-pass frequency response that is composed of a modified current-mode bi-quad (M 19-20 and C 2-3 ) [24], a first-order RC LPF (R 4 and C 4 ), and a first-order source followerbased LPF (M 23-24 and C 5 ) [25]. Figure 8 shows the simulated filtering characteristic of each block of the proposed RF front-end receiver. Considering the channel bandwidth of 1.25 MHz, the À1-dB bandwidth of the RF filters (Z RF1 and Z RF2 ) and the TIA with fourth-order LPF are 2 MHz, 2.4 MHz, and 2 MHz, respectively; for each block, the corresponding attenuations at a 3-MHz offset frequency are 5.8 dB, 4.2 dB, and 27.5 dB, respectively. ...
This paper proposes an IEEE 802.15.4m compliant TV white‐space orthogonal frequency‐division multiplexing (TVWS)‐(OFDM) radio frequency (RF) transceiver that can be adopted in advanced metering infrastructures, universal remote controllers, smart factories, consumer electronics, and other areas. The proposed TVWS‐OFDM RF transceiver consists of a receiver, a transmitter, a 25% duty‐cycle local oscillator generator, and a delta‐sigma fractional‐N phase‐locked loop. In the TV band from 470 MHz to 698 MHz, the highly linear RF transmitter protects the occupied TV signals, and the high‐Q filtering RF receiver is tolerable to in‐band interferers as strong as −20 dBm at a 3‐MHz offset. The proposed TVWS‐OFDM RF transceiver is fabricated using a 0.13‐μm CMOS process, and consumes 47 mA in the Tx mode and 35 mA in the Rx mode. The fabricated chip shows a Tx average power of 0 dBm with an error‐vector‐magnitude of < 3%, and a sensitivity level of −103 dBm with a packet‐error‐rate of < 3%. Using the implemented TVWS‐OFDM modules, a public demonstration of electricity metering was successfully carried out.
... Thus, merging more functions in one cascode cell for current-reuse becomes a prospective direction for power savings, while improving the performances due to less -to-and -to-conversions; both just generate noise and nonlinearity. This work introduces a compact linear equalizer featuring a current-reuse AI [15]. It is merged into the DFE core [see Fig. 3(a)] as the main tap path. ...
... Stacked atop input differential pair, there is an AI sharing the same bias current. The cross-diodeconnection of create a positive-feedback impedance converter [15], transferring the capacitive effect of at into an inductive effect at . The equivalent inductance is given by , where is the transconductance of . is realized as a MOS varactor for tuning. ...
This paper reports a full-rate direct decision-feedback-equalization (DFE) receiver with circuit techniques to widen the data eye opening with competitive power and area efficiencies. Specifically, a current-reuse active-inductor (AI) linear equalizer is merged into a clocked-one-tap DFE core for joint-elimination of pre-cursor and long-tail post-cursors. Unlike the passive-inductor designs that are bulky and untunable, the AI linear equalizer offers orthogonally tunable low- and high-frequency de-emphasis. The clocked-one-tap DFE resolves the first post-cursor via return-to-zero feedback data patterns for sharper data transition (i.e., horizontal eye opening), and is followed by a D-flip-flop slicer to maximize the data height (i.e., vertical eye opening). A 10-Gb/s DFE receiver was fabricated in 65-nm CMOS. Measured over an 84-cm printed circuit board differential trace with 23.3-dB channel loss at Nyquist frequency (5 GHz), the achieved figure-of-merit is 0.027 pJ/bit/dB (power consumption/date rate/channel loss). At 10-12 bit error rate under 27-1 pseudorandom binary sequence, the horizontal and vertical eye opening are 59.6% and 189.3 mV, respectively. The die size is 0.002 mm2.
... The current-mode Biquad [ Fig. 6(a)] proposed in [14] is an excellent candidate for current-reuse with the Blixer for channel selection. However, this Biquad can only generate a noise-shaping zero spanning from DC to MHz for -, where and are the Biquad's quality factor and 3 dB cutoff frequency, respectively. ...
... It implies can be leaked to the output via , penalizing the in-band noise. At even higher frequencies, the output noise decreases due to , being the same as its original form [14]. The signal TF can be derived from Fig. 8 with and without the is shown Fig. 8, showing about 0.1 dB improvement at the TT corner (reasonable contribution for a BB circuit). ...
Ultra-low-power (ULP)
radios have essentially underpinned the development of short-range wireless technologies [1] such as personal/body-area networks and Internet of Things.
... Thus, their area and power efficiencies are generally low, because a high selfresonant frequency demands a sufficient bias current to overcome the parasitic effects induced by the AI. Recently, it has been revealed that a differential AI could be more effectively emulated via a PFIC, especially for analog circuits, such as filters [7]. This brief studies, for the first time, the versatility of PFIC-based AI in the 10-GHz range, using a mainstream 65-nm CMOS process. ...
A 0.0015-mm $^{2}~1.28$-mW single-branch analog equalizer is demonstrated in 65-nm CMOS for 10-Gb/s input/output links. Instead of using passive inductors that are untunable and unscalable with technologies, gain compensation here is optimized via a tunable and current-reusable active inductor (AI). This AI incorporates a positive-feedback impedance converter with only two MOSFETs and one MOS varactor. Together with the use of: 1) negative Miller capacitors to optimize the pole-zero composition and 2) tunable resistive source degeneration to adjust the low-frequency losses, the analog equalizer recovers an eye-opening rate of minimally 30% up to 10 Gb/s over a pair of 60-cm FR4 microtrip traces. The data Pk-to-Pk jitter is <24 ps, and the RMS jitter is < ps, over a number of pseudorandom bit sequence patterns ( $2^{7}$ –1, $2^{15}$ –1, and $2^{31}$ –1).
... To enlarge the dynamic range and BW tuning range, an elevated V DD was employed as in [9] and [10], ensuring adequate device overdrive voltages against a wide range of bias current. Operated at a 3-V V DD and due to the self-bias nature of the SFAI, the simulated dc-level variations [Fig. ...
A single-branch third-order low-pass filter with an ultracompact die size and extensive bandwidth (BW)-power scalability is described. It unifies a source follower, a stackable floating active inductor, and a feedforward capacitor to constitute a transistorized-LC-ladder topology with a stable pole-zero transfer function over a wide range of tunable BW. Differentially, only eight transistors and five untuned capacitors are required. Fabricated in 0.18-mu m CMOS, the prototype occupies 0.014-mm(2) die size. By scaling the bias current (and, hence, the power), the flexible BW measures 0.8 kHz at 1.25 nW and 0.94 GHz at 3.99 mW.
... It is a differential amplifier with an embedded current-reuse AI. This AI was employed as a sub-circuit of a low-frequency lowpass filter reported in [3]. This work advances its use in a wideband S2D with large-signal operation, also revealing its differential balancing property. ...
An extremely compact, doubly balancing single-to-differential converter (S2D) for high-speed wireline systems is reported. It incorporates a two-stage topology with `coarse balancing' in the first stage and `fine balancing' in the second stage by adopting a compact `positive-feedback active inductor' that simultaneously boosts the signal bandwidth. Fabricated in 65 nm CMOS, the S2D measures <; 1.1% data cross error and <; 3.4 ps RMS jitter up to a 14 Gbit/s data rate. The die occupies 0.0012 mm2 and consumes 8 mW.
... A current-domain Biquad [5] can be stacked atop the I/Q mixers for effective filtering [4]. However, its noise-shaping zero is located at DC, unsuitable for low- IF RX. ...
Nanoscale CMOS offers sufficiently high ft and low Vt favoring the design of ultra-low-power wireless receivers (RX) via stacking the RF-to-BB functions in one cell, while sharing the smallest possible bias current. Also, the signals can be conveyed in the current domain to enhance the area efficiency (i.e., no AC-coupling capacitor), RF bandwidth and linearity at those inner nodes. The 2.4GHz LMV cell [1] for ZigBee RX is an example that unifies one LNA, two mixers (I/Q) and one VCO. The power is low (2.4mW), but the NF, gain and S11 are sensitive to its external high-Q inductor that performs narrowband input match and passive gain boost. Although one VCO (i.e., one inductor) can save area and power, the I/Q generator has to be placed in the RF path. Realized as a gm-C network, it suffers from a 3dB gain loss deteriorating the RX NF (12dB), while rendering the I/Q accuracy more susceptible to process variation.
... For a specified resonant frequency, 0s , the required g m1 , g m1,req , can be derived as Eqs. (13,14) by referring to Eq. (2,11,12). ...
... From Eqs. (13,14) and the generalized g m equation of the transistor in the saturation region (g m = 2I D / V ov ), the required power consumption for the specified 0s can be represented as ...
In this paper, the relationship between the bandwidth (BW) and power efficiency of a source follower based (SFB) filter is quantitatively analyzed, and a design methodology for a SFB filter for optimized BW - power consumption is introduced. The proposed design methodology achieves a maximum BW at a target quality (Q) factor for the given power consumption constraint by controlling design factors individually. In order to achieve the target BW from the maximized BW, a tuning method is introduced. Through the proposed design methodology, a fourth order Butterworth filter was implemented in 0.18 μm CMOS technology. The measured BW, power consumption, and IIP3 are 100 MHz, 33,iW, and 9 dBm, respectively. Compared with other filter structures, the measured results show high BW -power efficiency.
