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Physical layout and block diagram of LTARS2018.

Physical layout and block diagram of LTARS2018.

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Figure 1. Physical layout and block diagram of LTARS2018.
Technological parameters and requirements for the LTARS2018.
Development of Low Temperature Analog Readout (LTARS 2018) for LAr-TPCs
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  • Nov 2022
We have developed an analog front-end electronics, called LTARS2018[1], for TPC-applications, targeted at dual-phase liquid argon TPCs for neutrino experiments and negative-ion μ - TPCs for directional dark matter searches. This electronics have a wide dynamic range for input charge up to 1600 fC and a function to output a signal with an appropriat...
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... physical layout of the LTARS2018 implemented in the Silterra 180 nm CMOS technology and the block diagram of each channel is shown in Figure 1. The chip size is 2.5 mm × 5 mm. ...

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