Performance comparison between a single core and multi-core processor 

Context in source publication

Context 1

... order to track the continuing performance improvement following Moore’s low, successive technologies have relied on scaling of different device and interconnect parameters. Historically, these performance gains have been accomplished by efficient exploitation of sophisticated process technology, innovative architecture or micro-architecture [2]. To keep on the circuit speed, focus is mainly given on increasing operating frequency. Device dimensions have been scaled to support higher integration density for greater functions. However, this scaling brings in several critical challenges in current sub- 65nm technology. Although power supply has been scaled to keep the dynamic power at bay, due to the aggressive scaling of MOS geometry leakage power has been a major part of total power. Growing device components further aggravates the heat generation in a small chip. Therefore, thermal challenges have appeared as one of the major challenges to the successful advancement of CMOS technology [6]. A new approach called “parallel processing” was proposed in early 1990s to save power [9]. Since then, this method has gained wide acceptance among the architecture designers for which almost every processor now a days runs on this principle. However, this approach can’t alone continue supporting growing speed of microprocessors. Clock frequency must be increased which in turn generates more heat in a processor. This is the main reason for all commercial processors to stick around 4GHz. Considering the growing concern for power dissipation, the concept of multi-core processor is a new step forward and it has become the technology for current and next decades [11], [18]. A multi-core chip-level processor combines two or more independent cores into a single die. Thus a Dual-core processor contains two cores; a Quad- core processor contains four cores and so on. A multi-core processor implements multi-processing units on a single physical package. One basic difference between single processor and multi-core processor is that a single processor has a unique L1 cache along with a L2 cache where as each independent processor in a multi-core system has a common shared L2 cache in addition to an individual L1 cache. In a single core processor, 45nm technology is currently in production and next come 32nm, and 22nm and most likely 10nm node is the limiting technology node considering the strong quantum effects. Consequently, multi-core processor is a promising architecture technique. IBM first introduced multi-core processor chip, Power4 in 2001 [15] through which designers were able to achieve much greater communication bandwidth and resulting performance. In mid-2006, Intel reached new levels of energy-efficient performance with their Intel Core TM 2 Duo processors using 65 nm technology and latest micro- architecture [2]. Although it has been a frequently used architecture, numerous challenges involve accordingly and they must be addressed by the researchers. The rest of this paper is organized as follows. Section II briefly gives some major advantages of multi-core processor. It is concluded that multi-core processors become the standard for delivering greater performance, improved performance per watt and new capabilities across different electronic applications. Section III describes the leading interconnect challenges in multi-core processors. Challenges incurred by design automation and verification and software adaptability have been briefly studied in section IV and V respectively. Finally section VI wraps up the paper. The key driving force to adopting multi-core processor architecture was to address power and cooling challenges. Figure 1 gives performance comparison between a single core and multi-core processor [2]. This analysis which is performed based on Intel tests using the SPECint2000 and SPECfp2000 benchmarks reports that multi-core processors perform much better than a single core processor and it is projected that relative advantage of multi-core system will enhance over the next couple of years. Historically chip manufacturers have met the demand for increasing processor speed by boosting up the operating clock frequency along with the higher integration density. This approach has resulted in uncontrollable heat dissipation in current technology node. With heat rising incrementally faster than the rate at which clock signal propagates through the processors, it has prompted the processor designers for alternative methodologies. Multi-core processors take advantage of a fundamental relationship between power and frequency. By incorporating multiple cores, each core is able to run at a lower frequency, dividing power among them normally given to a single core. The result is a big performance increase over a single core processor. It can be observed that increasing clock frequency by 20% to a single core delivers a 13% performance gain, but requires 73% greater power. Conversely, decreasing clock frequency by 20% reduces power usage by 49%, but causes only 13% performance loss [2]. If a second core is added into the single core architecture, it results in a dual-core processor that at 20% reduced clock frequency; it can effectively deliver 73% more performance while using approximately the same power as a single-core processor at maximum frequency. As stated earlier, each single processor core in a multi- core architecture has its unique L1 cache and all processors in the die share a common L2 cache. Therefore, number of caches and memories required become less than if single core processor is used for the equal number of jobs that need to be performed. For example, Intel Advanced Smart Cache works by sharing the L2 cache among cores so that data are stored in one place that each core can access. Sharing L2 cache enables each core to dynamically utilize even up to 100% of available L2 cache, thus optimizing cache resources [2]. Intel® Smart Memory Access improves system performance by optimizing available data bandwidth from the memory subsystem and hiding the latency of memory accesses through two techniques: a new adaptability called memory disambiguation, and an instruction pointer-based pre-fetcher that fetches memory contents before they are requested [2]. C. Performance enhancement by multi-threading Along with parallel processing method, multi-threading technology is extensively used in single core processor. According to this approach, on a single processor, multithreading generally works on the principle of time- division multiplexing which is much similar to the parallel execution of multiple tasks where the processor switches between different threads [13]. This context switching happens so fast that it creates the illusion of simultaneity to an end user. On a multiprocessor system, threading can be achieved via multiprocessing, where as different threads and processes can run simultaneously on different processor cores. Threading a task in parallel processing machines thus not only increases the number of tasks executed per unit time but also enhances the accuracy of the task. Consequently, it is obvious that significant performance improvement can be achieved using multi- core systems coupled with advances in memory, I/O, and storage devices. Although device performance in a single processor has increased with the continuous scaling technology parameters over the generations, interconnect performance has degraded since interconnect scaling exhibit exactly opposite trend. Therefore, the overall performance of a microprocessor is determined by interconnect characteristics [4]. The main bottleneck associated with the interconnection network of multi-core processor is the interfacing of different cores in a single die. Several interconnection mechanisms have been proposed in [10] to spice up the interconnect performance. Among them, a shared bus fabric (SBF) that provides connection to various modules with the capabilities of coherence source and sinking, a point to point link that connects two SBFs and a cross bar connection system are most commonly used. A shared bus fabric is a high speed link which can communicate data between processors, caches, I/O and memory in a multi-processor system. The effectiveness of such an approach depends on the probability that an L2 miss is serviced on a local cache (an L2 connected to the same SBF), rather than a cache on a remote SBF. It is not easy to maintain this condition in a complex multi-core system. Another problem is that the interconnect fabric itself is large and power-hungry, consuming resources that would otherwise be available for more cores and caches. ...