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Network on chip (NoC) has been proposed as an appropriate solution for today’s on-chip communication challenges. Power dissipation has become a key factor in the NoCs because of their shrinking sizes. In this paper, we propose a new encoding approach aimed at power reduction by decreasing the number of switching activities on the buses. This approa...
Citations
... Power dissipation is introduced as an important issue in NoCs because of advanced VLSI technology [4]. Researchers proposed many different approaches to decline energy consumption in NoCs [5]- [19]. A great deal of research has been conducted to reduce the energy dissipation of NoCs with using optimized algorithms [6]- [15]. ...
... A great deal of research has been conducted to reduce the energy dissipation of NoCs with using optimized algorithms [6]- [15]. Another approach to minimize the power dissipation is low power encoding algorithms [5], [16]- [19]. These methods try to reduce the number of switching activities and dynamic power dissipation. ...
... It should be mentioned that the power of encoder and decoder are the overhead of low power encoding algorithms which must be considered to evaluate its efficiency. Researchers in [5] present a new low power encoding algorithm for on chip networks which is called MFLP (Most Frequent Least Power). ...
... There is also a contribution that is an encoding technique based on a tree algorithm called Most Frequent Least Power (MFLP). 21 The purpose is to reduce the switching activity by coding the most frequent data with the least consuming words (that contain the minimum number of '1', inducing less transitions). The amount of transitions is reduced, however cross transitions can still occur. ...
Networks-on-Chip (NoCs) are recognized to be the solution to address the communication bottleneck in many-core systems. As the NoC represents a significant part of the system power consumption, NoC energy consumption optimization is a challenging task. In this paper, we propose a shielding technique enhanced for NoCs and we evaluate its efficiency by comparing it to the best achievable energy saving. Then, we propose a shielding generator and its architecture to balance performances and energy saving. Results are carried out on a NoC simulator under synthetic traffics and application based traffics. These results show up to 13% of total energy saving and the impact on performances can be reduced by 33% compared to already existing shielding techniques.
This article shows one of the potential applications of multiple-valued logic (MVL) for low-power data transfer in a network-on-chip (NoC). Dynamic power accounts for a large portion of the total chip interconnect power. This article combines ternary limited-weight codes (TLWCs) with quaternary transition signaling (QTS) to present a low-power bus encoding method. By this way, voltage swing and switching activity factor, the two main reasons for dynamic power consumption, are targeted. Not only does the proposed method reduce power, but it also accelerates data transmission because it compacts every four bits of information in only three ternary digits. Full details of the required components, such as a modulator, a demodulator, a quaternary flip-flop, and a quaternary repeater, are given. All circuits are simulated by Synopsys HSPICE and 32-nm CMOS technology. Then, the HSPICE results are applied to the Access Noxim simulator for NoC-level simulations. The results demonstrate that in a 3-D network with 12
$\times$
12
$\times$
4 nodes, the proposed MVL bus encoding decreases the total energy and the average global delay by at least 9.25% and 31.39%, respectively, compared to when binary minimal encoding is used. Finally, the proposed model reduces the effects of crosstalk noise because it eliminates rail-to-rail transitions.
Network on Chip (NoC) is growing technology whereby multiprocessor state interconnect patterns are formed. NoC technology is adapted to support a variety of multiprocessor requirements. The existing designs do not support the growth requirements of user applications. Because of the complex routing connections, several problems exist about traffic congestion and Power consumption contributing to a network's low efficiency. Traffic Congestion, Power consumption, and latency are a significant concern in Network on Chip architectures because of various dynamic routing connections. The existing models do not consider all the above-mentioned factors and struggle to achieve higher performance. The previous methods do not trigger the circuits according to the traffic condition and maximum power consumption. For this, the proposed High-Speed Virtual Logic Network on Chip router architecture is utilized for controlling the traffic congestion and deadlock issues, reduce the latency by selecting the minimal interval paths. In this research work, an architecture containing a Virtual router is introduced which yields low power consumption resulting in improving the performance of a network by performing the routing in a diagonal direction along with the other directions. Also, the method selects an optimal path according to various conditions that neglect the unnecessary triggering of chips which reduces the power consumption. The proposed model considers the dynamic congestion and route available to perform routing with the least power consumption. By comparing both the architectures, VC Router outperformed 15% of low power consumption for the 8-bit system, 10% of low power consumption for the 16-bit system, and 22% of low power consumption for the 32-bit system.
In the fast nanosilicon revolution era, network-on-chip (NoC) architecture offers a significant research solution to on-chip multiprocessor-based real-time applications. As the number of cores increases, power consumption of the resources of NoC also increases. Links are the major power dissipator in NoC architecture owing to switching activity of data bits communicated through them. The performance of data communication links in NoC is strongly dependent on the factor of power dissipation. An efficient coding method is needed to reduce both coupling and self-switching activity of data bits of NoC links. In this work, an improved low-power encoding algorithm for serial links is proposed to reduce switching transition for any random data pattern making them more suited to real-time applications. The proposed encoding algorithm is coded, simulated and verified its area and power performance using Synopsys tools utilizing UMC 90 nm technology. Experimental results have shown that it provides on average 48.83% of switching activity reduction for any real-time applications.
Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex constraints on the overall design. This paper discusses the challenges faced, when designing NoCs for real-time applications. Contributions in this area are surveyed on the level of guaranteed Quality-of-Service (QoS) support, adaptivity, and energy efficient techniques. Furthermore, the evaluation methodologies and experimental performance measurements of real-time NoCs are examined. This survey provides a comprehensive overview of existing endeavors in real-time NoCs and gives an insight towards future promising research points in this field.
