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PMOS 2 T gain cell structure and its layout based on cell-body voltage transition. (C_BD: Cell-body, BL_W: Write-bitline, BL_R: Read-bitline, WL_W: Write-wordline, WL_R: Read-wordline, SN: Storage node, STI: Shallow trench isolation)
Source publication
This study presents a novel approach which enhances the data retention capability of PMOS gain cell based embedded DRAM. The proposed circuit technique utilizes a parasitic capacitance between the cell storage node and the common n‐well body. During the write operation, an up‐down voltage transition to the n‐well increases the cell storage retentio...
Contexts in source publication
Context 1
... outline the bit-cell operational principle with the technique used to achieve high bit retention in a native logic process. Figure 1 depicts the PMOS-only 2 T gain cell structure and its layout designed in a 0.13-μm logic CMOS process. The memory cell is composed of a high threshold-voltage (V TH ) write-PMOS (M1) and a normal-V TH read-PMOS (M2). ...
Context 2
... memory is fully functional down to 850 mV. The maximum clock frequency mea- sures 200 MHz for 1.2 V. Figure 10 shows the power consumption according to clock frequency. The memory operating with C_BD voltage transition has almost 9.6% power overhead because of C_DB boosting. ...
Context 3
... memory operating with C_BD voltage transition has almost 9.6% power overhead because of C_DB boosting. Figure 11 displays the bit-to-bit retention time from an 8-kbit sub-array for different supply voltages at a high temperature of 85°C. We have measured the retention time at the maximum frequency by detecting the time interval during which the stored information is read cor- rectly after writing a bit data. ...
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Citations
... 5 Gain-cell embedded dynamic random-access memory (GC-eDRAM) has been popular as an alternative to conventional static random-access memory (SRAM) because of its scalability, higher area density, inherent two-port operation, non-destructive read operation, and low leakage consumption compared to SRAM. 6 Nonetheless, the major drawback of gain-cell memories is the need for periodic refresh cycles, resulting in a considerable amount of refresh power and thus retention power consumption that limits the availability percentage. Consequently, the data retention time (DRT) improving reduces power consumption. ...
... The use of LP technology for the write transistor results in higher DRT since the transistors are in the primary data failure path. 6 In the proposed design, WWLn and WWLp are used to neutralize the effects of the applied CF and CI to the SN due to the opposing CI and CF effects from the PW and NB transistors due to the occurrence of the de-assertion of the wordlines. 9 Given that both ptype and n-type transistors are in the data write path, '1' and '0' are only written up to V DD -V Tn and V Tp , respectively. ...
Conventional static random-access memory (SRAM) suffers from high leakage power in advanced complementary metal-oxide-semiconductor nodes. Meanwhile, gain-cell embedded dynamic random-access memory (GC-eDRAM) is an area-efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field-effect transistor (FinFET)-based 5T GC-eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth-consuming refreshes of GC-eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain-cell design is based on the FinFET, which overcomes short-channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all-nMOS fully depleted-silicon on insulator (FD-SOI) gain cell to ensure the static retention of both “1” and “0” data. The 2-kB array was simulated by employing a 7-nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all-nMOS GC-eDRAM cell in a 28-nm FD-SOI technology.
