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![Table 1 . Biasing methods for high-V TH PMOS and NMOS [61].](publication/314104743/figure/tbl1/AS:668882775859217@1536485489536/Biasing-methods-for-high-V-TH-PMOS-and-NMOS-61_Q320.jpg)
Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during th...
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It is well known that there is a trade-off between performance and power consumption in onboard computers. The fault-tolerance is another important factor affecting performance, chip area and power consumption. Involving special SRAM cells and error-correcting codes is often too expensive with relation to the performance needed. We discuss the poss...
Branch prediction units are key performance components in modern microprocessors as they are widely used to address control hazards and minimize misprediction stalls. The continuous urge of high performance has led designers to integrate highly sophisticated predictors with complex prediction algorithms and large storage requirements. As a result,...
Citations
... If source and bulk of NMOS are grounded and drain is connected to V DD , then diode formed at drain junction becomes reverse biased (Fig. 2). This results in reversed biased leakage current from drain to substrate [30]. This leakage can be controlled using SOI technology where a thin layer of insulator (SiO 2 ) is introduced within the substrate region which bars any flow of charge carriers from drain to substrate [31]. ...
Leakage current in a MOS device has become a bottleneck with the technological growth of semiconductor industry. As the device is scaled down to sub nano meter regime, leakage current components becomes comparable to that of ON-state current. The focus of this paper is to investigate a detailed comparative analysis of various leakage currents present with or without short channel effects. The overview of the various parameters affecting the leakage currents has been extensively explored. Further, various techniques to minimize the leakage have also been considered. A quantitative analysis of leakage affecting the various short channel devices including the junctionless transistor has been performed and compared.
... * 2T inverters were not included in PDP and area calculations for XORs. . . . . [79] and b) Cross Section of single gate n-channel MOSFET shown with currents caused by SCE [11]. [87] b) Energy vs. position diagram of a wave incident to a finite potential barrier [79] 12 The energy band diagram of metal-semiconductor junction a) before b) after the contact is formed. ...
... However, in short channel case, this barrier gets lower by depletion from the drain side shifting the device threshold voltage to lower than desired. This effect can be seen from drain current vs. gate voltage (Id-Vg) plots [10][11][12] and leads to higher subthreshold leakage current in comparison with the long channel case. Another consequence of DIBL in ultra-short devices is band to band tunneling (B2BT), that is the transfer of source (drain) electrons (holes) to empty hole (electron) states on the drain (source) side by tunneling through the much lower and thinner potential barrier. ...
... 3: a) Electron wave functions during tunneling through finite energy barriers[79] and b) Cross Section of single gate n-channel MOSFET shown with currents caused by SCE[11].theory predicts that if charge carriers are subject to a sufficiently thin potential barriers (typically tens of nanometers) an important percentage of incoming charge carriers could tunnel through that potential barrier although they possess a lower amount energy than the potential barrier. ...
As modern Complementary Semiconductor Metal Oxide (CMOS) technology is approaching to the end of scaling limits projected by
Moore’s Law, researchers are in a constant pursuit for alternative solutions for the continuation of this trend. Although this proposition will likely require revolutionary technologies as alternatives to replace Si CMOS, the time and cost of such dramatic replacements make industry rather reluctant to accept them as immediate solutions. Thus, designers still search ways to re-optimize and further improve the current dominant CMOS devices and the integration methods, until
the proposed exclusive technologies such as III-V semiconductors on silicon, 1D/2D channel materials like dichalcogenides, carbon nanotubes, graphene or single electron transistors are fully developed. In this evolutionary approach, Schottky barrier (SB) FinFETs are excellent candidates to address the needs of the CMOS scaling in the next few nodes and provide the time and extra room needed. In this work, the SB-FinFETs are introduced, developed and optimized for the needs of sub-10nm CMOS integration using a novel metal work-function engineering (WFE) approach that results in substantial
savings in area and power, while retaining competitive performance for logic switching.
Guided by the versatile WFE approach, SB-FinFETs are designed to operate as ambipolar devices with equal current drive and high ION/IOFF ratio (> 107) necessary for optimal logic switching. Use of multiple (typically up to four) work-functions in the contacts of SB-FinFETs allow for unique local (gate-level) threshold adjustments and
functional (module-level) modifications to design novel ultra-compact digital circuits with only two transistors (2T). Following the proposed WFE design methodology with independent-gate SB-FinFETs, the performance improvements in sub-10nm circuits are found to be up to 50% reduction in static (NAND,NOR,XOR) gate area, 80% in transistor
count at multi-input gates and reconfigurable modules. The nature and extent of area and power advantages will depend on the complexity and style of logic implementation. We propose novel compact static CMOS logic gates with a typically ×5 to ×10 reduction in dissipated power and ×3 to ×5 reduction in switching speed, resulting power×delay products (PDP) comparable to conventional p/n junction FinFET devices found in CMOS products today. Thus the proposed methodology trades speed for power and area, which is quite acceptable for sub-10nm CMOS design that suffers from the lack
of both. Based on these novel gates and extended utilization of WFE, the area and power gains was further expanded to larger combinational and sequential logic circuits such as full-adders, multiplexers, latches and flip-flops.
In an effort to truly explore the capabilities of WFE as applied to SB-FinFETs, ultra-compact reconfigurable logic circuits with 2T,3T and 4T were also designed. These circuits, which allow the gate function to change between multiple outcomes by use of select input(s), require insights to inner states accessible to a given 2T/3T/4T topology
when work-functions are uniquely set. They result in ×3 to ×10 reduction in dissipated power, ×2 to ×15 reduction in area overhead. At the same time there is ×2 to ×5 reduction in switching speed, while maintaining still competitive performance in terms of PDP.
Although WFE is explored in this work in the context of SB-FinFETs, the methodologies developed here can be applied to any other device technology that may benefit from judicious use of multiple metal work-functions to create more agile and compact logic switching.
... The leakage current is one of the major factors responsible for the power consumption in the SRAM cell [11] [13]. Different components of leakage currents in SRAM cells are subthreshold leakage current (Isub), gate leakage current (Igate) and junction leakage current (Ijn) [25]. Ideally, during a standby mode of SRAM cell, the unwanted flow of current is leakage current which flows in different situations consumes more power. ...
... This paper analyzes the impact of such resistive defects on the behavior of low-power 6T-SRAM cells and evaluates the effectiveness of different test methods. This study specifically considers the effects of such defects when the backbias technique [5] is employed to reduce leakage, also evaluating the impact of current consumption on the memory cell. ...
This paper compares different types of resistive defects that may occur inside low-power SRAM cells, focusing on their impact on device operation. Notwithstanding the continuous evolution of SRAM device integration, manufacturing processes continue to be very sensitive to production faults, giving rise to defects that can be modeled as resistances, especially for devices designed to work in low-power modes. This work analyzes this type of resistive defect that may impair the device functionalities in subtle ways, depending on the defect characteristics and values that may not be directly or easily detectable by traditional test methods. We analyze each defect in terms of the possible effects inside the SRAM cell, its impact on power consumption, and provide guidelines for selecting the best test methods.
... Введение. В современных сверхбольших интегральных схемах (СБИС) особое место занимают статические оперативные запоминающие устройства (СОЗУ), которые составляют 80...85% общей площади СБИС, а их доля в производстве СБИС -примерно 60% [1]. При проектировании СОЗУ актуальной проблемой является уменьшение энергопотребления, которое в основном зависит от архитектуры СОЗУ, схемотехнических и технологических решений запоминающих элементов (ЗЭ) и схем управления. ...
... На рис.1 приведены тенденции роста мощностей статического и динамического компонентов в зависимости от технологических норм. Как видно из рисунка, статическая мощность растет быстрее при малых технологических нормах и становится соизмеримой с динамической [1,2]. ...
Обоснована актуальность минимизации потребляемой мощности статических оперативных запоминающих устройств на основе комплементарных металл-оксидполупроводниковых (МОП) структур. Приведена тенденция увеличения энергопотребления в зависимости от технологических норм, откуда следует, что компонент статической мощности при малых технологических нормах быстрее нарастает и становится соизмеримым с компонентом динамической мощности. Исследованы типовая структурная схема статического оперативного запоминающего устройства и ее основные узлы. Для расчета общего энергопотребления статических оперативных запоминающих устройств приведено соответствующее выражение. В результате анализа технической литературы выявлены выражения, соответствующие потребляемой мощности статического оперативного запоминающего устройства и ее основных узлов, которые позволяют оценить распределение потребляемых мощностей между разными узлами, а также уменьшить энергопотребление на этапе раннего проектирования за счет выбора структурных параметров запоминающего устройства. Рассмотрены структура межсоединений и ее модель задержки. Приведены соответствующие выражения для расчета сопротивлений и емкостей транзистора на основе МОП и для межсоединения. На основе результатов исследования предложена задача оптимизации, которая, по сути, является задачей нелинейного программирования. Предложены условия, необходимые для оптимизации, представляющие собой систему, состоящую из двух нелинейных трансцендентных уравнений, которую следует решить численным методом с использованием программного пакета MATLAB. Для решения задачи требуется наличие приближенной исходной точки, которая выбирается с учетом физического смысла задачи. В результате решения задачи получается локальная минимальная точка. Предложенные подходы позволяют реально решить задачу оптимизации.
... This paper analyzes the impact of such resistive defects on the behavior of low-power 6T-SRAM cells and evaluates the effectiveness of different test methods. This study specifically considers the effects of such defects when the back-bias technique [4] is employed to reduce leakage. ...
Low-power SRAM architectures are especially sensitive to many types of defects that may occur during manufacturing. Among these, resistive defects can appear. This paper analyzes some types of such defects that may impair the device functionalities in subtle ways, depending on the defect characteristics, and that may not be directly or easily detectable by traditional test methods, such as March algorithms. We analyze different methods to test such defects and discuss them in terms of complexity and test time.
... There are various types of leakage currents in a modern FET that contribute to the energy loss. They include subthreshold leakage current I sub , gate leakage I gate (gate-induced drain and source leakage currents, gate tunneling leakage currents through the bulk, source, and drain), and junction leakage currents I junction (p-n junction leakage currents at the drainsubstrate and source-substrate junctions) [33,34]. Although in the static state, the leakage currents of the two inverters may dominate the static energy consumption, during the write and read processes, the leakage of access transistors M5 and M6 also contributes to the total energy consumption. ...
... Although in the static state, the leakage currents of the two inverters may dominate the static energy consumption, during the write and read processes, the leakage of access transistors M5 and M6 also contributes to the total energy consumption. It can be roughly estimated that in a 6T cell about 40% of the total leakage is in the access paths of the cell [34]. ...
... LETs have a different turn-on mechanism and no SCEs of the FETs as discussed previously [10] and hence hybrid SRAMs will have minimal subthreshold leakage in the access paths. Since LETs do not have a physical gate, there will be neither any gate-related nor any SCE-induced leakage [33,34] in the access paths, and thus the leakage power consumption in the hybrid SRAM will be much reduced. Also, LETs do not have any unwanted p-n junctions or leakage paths to ground, hence the hybrid SRAM will also have no junction leakage [33,34] in the access paths, and the overall leakage will be much reduced. ...
A broad range of technologies have been developed for the chip and wafer scale connections and integrations of photonic and electronic circuits, although major challenges remain for achieving the single functional-unit-level integration of electronic and photonic devices. Here we use field-effect transistor/light-effect transistor (FET–
LET) hybrid 6T static random-access memory (SRAM) as an example to illustrate a novel approach that can alleviate three major challenges to the higher-level integration of the photonic and electronic elements: size mismatch, energy data rate, and cascadability. A hybrid 6T SRAM with two access FETs being replaced by LETs and the electrical word lines replaced by optical waveguides is proposed. This hybrid 6T SRAM is analyzed to reveal its potential in improvement of the switching speed and thus total energy consumption over the conventional 6T
SRAM. Numerical analyses, for instance, for a prototype 64 kB hybrid SRAM array, show a factor of 4 and 22 reduction in read delay and read energy consumption, and 3 and 4 in write delay and write energy consumption, respectively, when the access FETs are replaced by LETs. The potential impacts on the peripheral and assist circuits due to this hybrid structure and application of the LETs there are also briefly discussed.
... Power dissipation for dynamic and leakage rates according to the technology node[66] ...
... 60,61,62,63,64,65,66, and 67 are the RTL schematics of the blocks described in section 4.4. ...
Visible Light Communication (VLC) is an emerging field that has attracted attention in recent times, and it has been proposed as a complement or even an alternative to the conventional RF systems. The motivation for it is that the latter is suffering from a phenomenon known as RF spectrum crunch - due to the overuse of wireless communication in user-end applications. The first global attempt to standardize VLC was promoted by IEEE 802.15.7, which specifies the Physical (PHY) and Media Access Control (MAC) layers for short range VLC. It has three PHY layers (I, II, and III) with thirty operating modes suitable for a wide range of noisy channel conditions. The main element of them is the Forward Error Correction (FEC) component, which defines a set of error control techniques Reed Solomon (RS) codes, Interleaving, and Convolutional Codes (CC) employed to improve the capacity of the transmission channel. The goal of this master thesis is to propose a digital system that implements a FEC compliant with IEEE 802.15.7. The main outcome of this work is an open access Intellectual Property (IP) Core for the FEC, followed by a comprehensive explanation of its related Register Transfer Level (RTL) architecture. Most attempts for implementing a IEEE 802.15.7 compliant system is targeted to prototype applications in embedded platforms, whereas dedicated digital devices are more appropriate for the hardware realization of PHY layers. Moreover, the availability of reliable IP Cores for communication such as the FEC and its base blocks is scarce. These facts corroborate the demand for the intended work. Verification and synthesis of the resulting IP Core are carried out by both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) flows, and their results for size, timing and power consumption are analyzed and cross validated. IEEE 802.15.7 requirements for throughput and latency are also checked for the FEC IP Core, and they are fulfilled for most operating modes at the target device technologies. Improvements for the digital design architecture and methodology of the FEC IP Core are discussed at the end of this thesis, enabling opportunities for future academic and development project.
... For instance, for a standard n-FET fabricated on a p-type substrate, these include multiple gate related leakages: gate-induced drain and source leakage current, gate tunneling leakage current through the bulk, source, and drain; sub-threshold leakage current; punchthrough leakage current; and p-n junction leakage currents at the drain-substrate and source-substrate junctions [25], [26]. The leakage in a 6T cell depends on the logic state of the cell, the logic level of the word line, and the type of operation performed [27]. The total leakage current of an individual FET in the 6T cell may be modeled as [25], [27] : ...
... The leakage in a 6T cell depends on the logic state of the cell, the logic level of the word line, and the type of operation performed [27]. The total leakage current of an individual FET in the 6T cell may be modeled as [25], [27] : ...
... Although in the static state, the leakage currents of the two inverters dominate the static energy consumption, during the write and read processes, the leakage of access transistors M5 and M6 also contributes to the total energy consumption. From [27] it can be roughly estimated that about 40% of the total leakage is in the access paths of the 6T cell. If these leakages are severe, it may lead to a false read or write operation and affect the reliability of the 6T cell [25]. ...
There is an extremely high demand for a high speed, low power, low leakage, and low noise Static Random-Access Memory (SRAM) for high performance cache memories. The energy efficiency of SRAM is of paramount importance in both high performance and ultralow-power portable, battery operated electronic systems. In this article the factors affecting the over-all speed and total energy consumption of a conventional 6T SRAM cell/array with 6 FETs, particularly roles of access tran-sistors are analyzed to highlight the needs and directions for improvement. A hybrid 6T SRAM with two access FETs being replaced by light-effect transistors (LETs) and the electrical word lines replaced by optical waveguides (OWGs) is proposed. This hybrid SRAM is analyzed to reveal its potential in im-provement of the switching speed and thus total energy con-sumption over the conventional 6T SRAM. Numerical analyses of a prototype hybrid SRAM array of 64 KB show a factor of 7 and 34 reduction in read delay and read energy consumption, respectively; and 4 and 6 in write delay and write energy con-sumption, respectively, when the access FETs are replaced by LETs. The potential impacts on the peripheral and assist cir-cuits due to this hybrid structure and application of the LETs there are also briefly discussed.
... However, this will increase the required length of the device. 5. The proposed multi-bias approach to obtain optical modulation is not analyzed for varying electric field (dynamic characteristics) for the device and needs to be explore. ...
The development of electronic photonic integrated circuits (EPIC) has revolutionized inter/intra chip short-haul communication by replacing bandwidth-limited metal interconnects with high-speed optical interconnects. Silicon photonics is playing a major role in the growth of EPIC that enables the fabrication of various on-chip photonic components on matured CMOS platform. This dissertation investigates the guidance and electrical control of light in photonic structure-based engineered silicon for application in optical modulation. Here, mainly four issues are identified for an optical modulator working in depletion and injection modes of operation, those are: (i) RC time constant limited bandwidth in lumped electrode-based electro-optic modulator, (ii) weak coupling between RF and optical modes at higher microwave frequencies in traveling-wave electrode-based configuration, (iii) FSR limited and highly thermal sensitive optical characteristics in resonant based structure, and (iv) shifting of transmission dip/peak in resonance-based optical structure with applying an electric field.
A high-speed electro-optic modulator based on CMOS compatible silicon waveguide is proposed to improve coupling between RF and optical mode. The optical waveguide in silicon is formed by creating a slot in a rib structure that results in strong optical confinement with an acceptably low propagation loss. The proposed design of the slotted-rib waveguide with a traveling-wave electrode facilitates an efficient optical modulation in silicon. Taking the advantage of velocity matched between optical and microwave modes, a high-speed operation up to 70 Gbps with an extinction ratio of ≈ 4.9 dB is reported at a peak to peak voltage of 3 Vpp under a reverse bias of 4 V. An insertion loss of 3.1 dB is obtained for a 4 mm long device. However, moderate modulation efficiency remains a major issue with the proposed device structure.
The given issue of moderate modulation efficiency is considered in the next work, where optical modulation in silicon with high data rate and high modulation efficiency is proposed by a laterally separated vertical p-n junction. Two independent but synchronized p-n junctions that support the common optical mode are created by forming a slot waveguide structure. It provides a prominent way to enhance the light-material interaction necessary to achieve low VπL along with the low RC time constant which is crucial for the high-speed operation. The proposed device shows a high modulation efficiency of 0.74 V-cm for a 1.2 mm long device. The calculated intrinsic 3-dB bandwidth reaches up to ≈ 58 GHz at a reverse bias of 6 V. We show high-speed operation up to 25 Gbit/s for the device length of 600 µm with a simple lumped electrode configuration. The Traveling-wave electrodes as a coplanar waveguide are employed to further improve the speed performance of the device. By taking advantage of excellent velocity matching between optical group index and RF effective index, high data rate performance up to 100 Gbit/s is obtained with an extinction ratio of 2.4 dB. The proposed device opens new avenues for high speed optical interconnect on an SOI platform.
In order to achieve a compact on-chip device with a novel guiding mechanism, a silicon-based compact comb-like asymmetric grating is proposed as a thermally stable optical filter for multi-functional applications such as bio-sensor, electro-optic modulator, DWDM, etc. The device is designed and fabricated with a cavity section introduced between the two grating regions which are partially etched in the lateral direction to ensure the nonzero coupling of the fundamental and first-order modes in the propagation and counter-propagation direction. To demonstrate efficient optical guidance in the proposed device, refractive index sensing based on resonance shift in the spectrum is demonstrated with sodium chloride (NaCl) dissolved in DI water. In contrast to conventional Bragg grating where stopband lies in the transmission spectrum, the proposed device allows a single narrow passband transmission peak with a large Free Spectral Range (FSR) attributed to the engineered photonic bandgap of two modes present in the waveguide region. The device is deliberately designed such that slightly wide resonance peak is obtained that makes device operation thermally stable for a large temperature variation of ±15 K. A higher-order leaky mode with strong light-analyte interaction (due to long corrugation width) in the gratings governs high sensitivity of ≈ 352 nm/RIU for different concentrations of NaCl from 0% to 10% in the Deionized (DI) water with a small footprint area of 18 µm2 only. Proposed filter characteristics are well suited for multifunctional applications in integrated photonic devices. However, fabrication of the proposed device is complex due to the presence of two grating periods of nearly equal dimensions.
Further, to ease the fabrication complexity in the dual perturbed structure, next we proposed a tapered cavity coupled comb-like asymmetrical grating-based optical filter where both set of gratings are having an equal grating period and duty cycle. The narrow FWHM of 1.2 nm with a high extinction ratio of 14 dB is demonstrated in the fabricated device. In addition to the measured optical guidance mechanism, we theoretically investigate electrically tunable optical characteristics of the device by considering the two p-n junctions formed in both sets of gratings. Optical signal tunability is reported in two different ways: (i) resonance peak shift with an applied bias to one set of gratings, (ii) tuning of peak resonance intensity at a fixed wavelength using a programmable set of bias voltages at both the junctions. A high reduction of nearly 79% is achieved with the given multi-bias approach.
