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A programmable baseband processor architecture is presented. The architecture is based on a specialized DSP processor core and a number accelerators connected via a configurable network. The focus of this paper is the DSP core itself. A novel type of instructions operating on vectors of complex data is used. Implementation of a demonstrator chip an...
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... remaining computations relate to de-/mapping, channel coding, interleaving, scrambling and error checking. These are bit all manipulation operations, many of which do not lend them- selves to efficient implementation in software but may be very simple to implement using dedicated hardware. Fig. 1 gives an overview of the architecture. The system is con- trolled by a specialized processor core. The core is connected to a number of accelerators and interfaces via a configurable net- ...
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... An important aspect of our approach is our use of the SIMD VPU to implement our proposed SNOW3G and GFM64 instructions. Many SDR architectures employ multiple SIMD processing engines and/or pipelines with 16-bit or 32-bit data types [18][19][20][21][22][23][24]. We believe our design has the potential to be used in those architectures. ...
Software-defined radio (SDR) is a new technology transitioning from research into commercial markets. SDR moves hardware-dominant
baseband processing of multiple wireless communication protocols into software on a single chip. New cellular standards, such
as HSPA+, LTE, and LTE+, require speeds in excess of 40Mbps. SNOW 3G is a new stream cipher approved for use in these cellular
protocols. Running SNOW 3G in software on our SDR platform provides a throughput of 19.1Mbps per thread for confidentiality
and 18.3Mbps per thread for integrity. To have secure cellular communications in SDR platforms for these new protocols, the
performance of security algorithms must be improved. This paper presents instruction set architecture (ISA) extensions and
hardware designs for cellular confidentiality and integrity algorithms using SNOW 3G. Our ISA extensions and hardware designs
are evaluated for the Sandbridge Sandblaster™ 3011 (SB3011) SDR platform. With our new SNOW 3G instructions, the performance of confidentiality and integrity improve by
70 and 2%, respectively. For confidentiality, power consumption increased by 2%, while energy decreased by 40%. For integrity,
power consumption remained consistent, while energy decreased by 2%.
KeywordsCryptography–Software-defined radio–Computer architecture–SNOW 3G–Cellular security
Progress in wireless communications has led to an increasing number of standards such as WIMAX, 3GPP-LTE, DVB-T, DVB-H and more. This work presents a reconfigurable channel estimation engine for OFDM systems. The engine can support multiple channel estimation algorithms for many wireless standards. It can also support both 1D and 2D channel estimation algorithms. This is important because the large performance gain of 2D over 1D channel estimation algorithms, which can be up to 5dBs. Moreover, 1D algorithms are less complex than 2D algorithms and they are the best choice when there is a need to reduce the receiver processing power. The engine does not use any dividers for least square pilots estimation, and hence, the least square pilot estimator engine is less complex than other engines. Although the engine was designed and optimized for channel estimation algorithms, it can also be configured as an FFT engine, FIR engine and many more. The engine was synthesized on Altera Startix III EP3SC150 FPGA and performs the estimation process in 94 µsecond for the worst case parameters in all supported standards.
Software radio is hard to be implemented. This is because that existing general purpose digital signal processors (DSP) are not competent for the works with highly computing intensity and baseband processor has poor scalability and flexibility. In order to get over the disadvantages of general purpose DSP and the baseband processor, the article puts forward a novel architecture of reconfigurable stream processor along with application-specific instruction set for software radio. The simulation results of the proposed processor show that the reconfigurable structure provides instruction set extension which can process not only existing wireless communication standards but also new ones with high efficiency. The results also show that the stream oriented structure and the reconfigurable instruction set for software radio ensure processing high-speed baseband signals in real time. Compared with general purpose DSP, the processor gains improvement of computing performance from five to thirteen times. The main goal of the article is to propose an effective way of designing hardware with both high computational performance and enough adaptive ability for software radio.
The two implementation choices for the baseband part of wireless radios are the application-specific platforms (e.g. application-specific integrated circuits (ASICs)) and the programmable processors (e.g. digital signal processors (DSPs)). An application-specific instruction-set processor (ASIP) is a customised processor that bridges the gap between the two platforms. In this work, a novel implementation of the signal processing part of an orthogonal frequency division multiplexing (OFDM) baseband processor using three ASIPs is presented. The ASIPs provide novel architectures for the symbol chain, including fast Fourier transform, channel estimation subsystem and synchronisation subsystem. This design provides a close to DSPs level of flexibility, making it suitable for supporting all the modes of a large number of OFDM standards. In the meantime, the system maintains a performance level comparable to ASICs. This is demonstrated by providing post-layout results for 0.13 μm Taiwan semiconductor manufacturing company complementary metal-oxide semiconductor technology.
This paper reports the design and software implementation of a real-time digital baseband receiver compliant with the IEEE 802.11a standard on the AsAP2 platform, a DSP chip multiprocessor. The computational platform consists of an array of programmable processors and configurable accelerators interconnected in a 2-D mesh network that are well matched for implementing complex DSP and embedded systems such as wireless and video applications. The receiver has full functionality including frame detection, timing synchronization, carrier frequency offset compensation, and channel equalization. It supports all eight operational modes defined in the standard: 6, 9, 12, 18, 24, 36, 48 and 54 Mbps. The implementation is optimized such that the receiver can obtain a full 54 Mbps rate while using an array of 29 small processors plus Viterbi and FFT accelerators configured to operate at 590 MHz.
We present a novel software defined approach for designing and implementing common baseband processing tasks. Our focus is on exploring the algorithmic and architectural design spaces of 3G and 4G systems to identify the computational and geometric structures shared by diverse coding schemes, services and hardware platforms, and the efficient and flexible integration of these structures on innovative extensible hardware. With an existing protocol processor design framework as our starting point, we add flexibility to the physical layer of the radio application domain by defining a methodology and a hardware platform for designing programmable open wireless architecture-enabled device instances. The proposed methodology executes in two phases: (a) initial design, which is done to a single standard using our design principles and methods, and (b) extension phase where the system upgrade is done component by component. The approach standardizes control structures, component abstractions, implementation of the architecture itself as well as methods for interactive optimization. Thus, in both design phases there is only a need to consider changes in component functionality and connectivity. We demonstrate the approach by initially targeting digital television, and then extending the system with minimal effort to support GSM. The costs of the GSM extension in the system were an area increase of 2.4%, a power increase of 2.7% and four days in hardware design and verification.
Fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and number flexible accelerators, connected via a configurable network. Design choices are motivated by the inherent properties of the baseband algorithms used in different types of radio systems. A large degree of hardware reuse between algorithms and standards, careful selection of accelerators, and low memory cost allows very area and power efficient implementation of multi-standard radio baseband processors. A demonstrator chip for 802.11 a/b/g physical layer baseband processing was manufactured in 0.18 μm CMOS. The silicon area is 2.9 mm<sup>2</sup>, including all memories.
As data transfer rates become higher, general processor is not competent for works with high computing intensity in wireless communication area. The other hand, existing baseband processors lack adaptive ability to support new applications and newer versions of existing application. Thus the paper puts forward a novel architecture of reconfigurable stream processor along with application-specific instruction set for software radio. The main goal of the processor is to point out an effective way to designing hardware of software radio with high computational performance and adaptive ability. We achieve this by analyzing multi-stream modalities of advanced wireless communication standards, such as 3G and WLAN. Simulation results show that the processor with powerful calculational capability can adapt to applications of wireless communication area easily.
