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Three-dimensional die stacking increases integrated circuit (IC) density, providing increased capabilities and improved electrical performance on a smaller printed circuit board (PCB) footprint area. However, these advantages come at the expense of higher volumetric heat generation rates and decreased thermal and mechanical access to the die areas....
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... of (29) for the optimum spacing requires iteration but is easily handled with current equation solving software. If manual iteration is required, an initial guess of channel spacing equal to die thickness on the right hand side will provide convergence to within % in three iterations for - . Fig. 6 shows optimum spacings calculated using (29) over a range of die length and thickness with for saturated FC-72 at atmospheric ...
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A detailed sensitivity study was carried out on various key parameters from a high precision numerical model of a microelectronic package cooled by natural convection, to provide rules for the thermal modeling of microelectronic packages subjected to natural convection heat transfer. An accurate estimate of the junction temperature, with an error o...
Citations
... Several studies have been performed regarding passive cooling of electronic devices [1]-[3], but as their performance was increased over the last two decades, the aforementioned method is not the best option to be considered. ...
The present work investigates, by means of numerical simulations, conjugate heat transfer effects inside a computer chassis. The numerical simulations were conducted by the FLUENT commercial Computational Fluid Dynamics (CFD) software. The solution was obtained by solving the Navier-Stokes equations in a three dimensional computational domain. A validation case (with experimental data available) was used to determine which Reynolds-averaged turbulence (RANS) model is suited for the aforementioned configurations. The comparison with the experimental values of velocity and temperature profiles were in favour of the standard k-ε model. Regarding the study of a computer chassis, emphasis was given to the key components, such as the Central Processing Unit (CPU), which is cooled using fans. Several cooling schemes were studied based on available commercial configurations. The numerical results of temperature distribution on the heat sources and the air streamlines were analysed in order to evaluate each case and find out if there is a satisfaction of the operating conditions. In addition, through the CFD process, the problematic areas are revealed in order to consider improvements. The present study also introduces cooling schemes that could be beneficial for applications where cooling of
electronic components is needed.
Chip stacks are a crucial building block in advanced 3D microsystem architectures and can accommodate shorter interconnect distances between devices, reduced power dissipation, and improved electrical performance. Although enhanced conduction can serve to transfer the dissipated heat to the top and sides of the package and/or down to the underlying PCB, effective thermal management of stacked chips remains a most difficult challenge. Immersion cooling techniques, which provide convective and/or ebullient heat transfer, along with buoyant fluid flow, in the narrow gaps separating adjacent chips, are a most promising alternative to conduction cooling of three-dimensional chip stacks. Application of the available theories, correlations, and experimental data are shown to reveal that passive immersion cooling-relying on natural convection and/or pool boiling - could provide the requisite thermal management capability for 3D chip stacks anticipated for use in much of the portable equipment category. Alternatively, pumped flow of dielectric liquids through the microgaps in 3D stacks, providing single phase and/or flow boiling heat absorption, could meet many of the most extreme thermal management requirements for high-performance 3D microsystems. Use of deionized water is shown to provide an order of magnitude improvement in heat dissipation relative to the available dielectric fluids.
The rapid increase in on-chip heat fluxes and package heat density, accompanying the migration to nanoelectronics and 3D chip stacks, has placed thermal management squarely on the critical path for advanced product development. Innovative, cost-effective cooling techniques, combined in a synergetic way with more conventional approaches, must be developed if the benefits of the Moore's Law progression are to be realized. Following a brief discussion of the industry roadmap for IC packaging and review of chip package thermal management options, attention will turn to the application of solidstate thermoelectric refrigeration and the thermal characteristics of direct immersion cooling in dielectric liquids. The presentation will close with a discussion of the research challenges associated with the commercial implementation of on-chip thermoelectric coolers and direct liquid cooling.
