Optimized 4-2 compressor of [8]. 

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... next step. The correction constant ( n þ k bits) is selected to be as close as possible to the estimated value of the sum of these errors to reduce the error distance. A truncated multiplier with constant correction has the maximum error if the partial products in the n À k least significant columns are all ones or all zeros . A variable correction truncated multiplier has been proposed in [6]. This method changes the correction term based on column n À k À 1 . If all partial products in column n À k À 1 are one , then the correction term is increased. Similarly, if all partial products in this column are zero , the correction term is decreased. In [7], a simplified (and thus inaccurate) 2 Â 2 multiplier block is proposed for building larger multiplier arrays. In the design of a fast multiplier, compressors have been widely used [8], [9], [10] to speed up the partial product reduction tree and decrease power dissipation. Optimized designs of 4-2 exact compressors have been proposed in [8], [11], [12], [13], [14], [15], [16]. Kelly et al. [17] and Ma et al. [18] have also considered compression for approximate multiplication. In [17], an approximate signed multiplier has been proposed for use in arithmetic data value specula- tion (AVDS); multiplication is performed using the Baugh- Wooley algorithm. However, no new design is proposed for the compressors for the inexact computation. Designs of approximate compressors have been proposed in [18]; however, these designs do not target multiplication. It should be noted that the approach of [7] improves over [17], [18] by utilizing a simplified multiplier block that is amenable to approximate multiplication. Initially in this paper, two novel approximate 4-2 compressors are proposed and analyzed. It is shown that these simplified compressors have better delay and power consumption than the optimized (exact) 4-2 compressor designs found in the technical literature [8]. These approximate compressors are then used in the restoration module of a Dadda multiplier; four different schemes are proposed for inexact multiplication. Extensive simulation results are provided at circuit-level for figures of merit, such as delay, transistor count, power dissipation, error rate and normalized error distance under CMOS feature sizes of 32, 22 and 16 nm. The application of these multipliers to image processing is then presented. The results of two examples of multiplication of two images are reported; these results show that the third and fourth approximate multipliers yield an output product image that has a very high quality and resemblance to the image generated by an exact multiplier, i.e., excellent values for the average NED and the peak signal-to-noise ratio (PSNR) are found (for the PSNR more than 50db). The analysis and simulation results show that the proposed approximate designs for both the compressor and the multiplier are viable candidates for inexact computing. This paper is organized as follows. Section 2 is a review of existing schemes for (exact) compressors. The two new designs of an approximate 4-2 compressor are presented in Section 3. Multiplication and four different approximate multipliers are proposed in Section 4. Simulation results for the approximate compressors and multipliers are provided in Section 5. The application of the proposed approximate multipliers to image processing is presented in Section 6. Section 7 concludes the manuscript. The main goal of either multi-operand carry-save addition or parallel multiplication is to reduce n numbers to two numbers; therefore, n À 2 compressors (or n À 2 counters) have been widely used in computer arithmetic. A n À 2 compressor (Fig. 1) is usually a slice of a circuit that reduces n numbers to two numbers when properly replicated. In slice i of the circuit, the n À 2 compressor receives n bits in position i and one or more carry bits from the positions to the right, such as i – 1 or i – 2. It produces two output bits in positions i and i þ 1 and one or more carry bits into the higher positions, such as i þ 1 or i þ 2. For the correct operation of the circuit shown in Fig. 1, the following inequality must be satisfied where c j denotes the number of carry bits from slice i to slice i þ j . A widely used structure for compression is the 4-2 compressor; a 4-2 compressor (Fig. 2) can be implemented with a carry bit between adjacent slices ð c 1 1⁄4 1 Þ . The carry bit from the position to the right is denoted as c in while the carry bit into the higher position is denoted as c out . The two output bits in positions i and i þ 1 are also referred to as the sum and carry respectively. The following equations give the outputs of the 4-2 compressor, while Table 1 shows its truth table. The common implementation of a 4-2 compressor is accomplished by utilizing two full-adder (FA) cells (Fig. 3) [8]. Different designs have been proposed in the literature for 4-2 compressor [8], [11], [12], [13], [14], [15], [16]. Fig. 4 shows the optimized design of an exact 4-2 compressor based on the so-called XOR-XNOR gates [8]; a XOR- XNOR gate simultaneously generates the XOR and XNOR output signals. The design of [8] consists of three XOR- XNOR (denoted by XOR Ã ) gates, one XOR and two 2-1 MUXes. The critical path of this design has a delay of 3 D , where D is the unitary delay through any gate in the design. In this section, two designs of an approximate compressor are proposed. Intuitively to design an approximate 4-2 compressor, it is possible to substitute the exact full-adder cells in Fig. 3 by an approximate full-adder cell (such as the first design proposed in [2]). However, this is not very efficient, because it produces at least 17 incorrect results out of 32 possible outputs, i.e., the error rate of this inexact compressor is more than 53 percent (where the error rate is given by the ratio of the number of erroneous outputs over the total number of outputs). Two different designs are proposed next to reduce the error rate; these designs offer significant performance improvement compared to an exact compressor with respect to delay, number of transistors and power consumption. As shown in Table 1, the carry output in an exact compressor has the same value of the input c in in 24 out of 32 states. Therefore, an approximate design must consider this feature. In Design 1, the carry is simplified to c in by changing the value of the other eight outputs. Since the Carry output has the higher weight of a binary bit, an erroneous value of this signal will produce a difference value of two in the output. For example, if the input pattern is “01001” (row 10 of Table 2), the correct output is “010” that is equal to 2. By simplifying the carry output to c in , the approximate compressor will generate the “000” pattern at the output (i.e., a value of 0). This substantial difference may not be acceptable; however, it can be compensated or reduced by simplifying the c out and sum signals. In particular, the simplification of sum to a value of 0 (second half of Table 2) reduces the difference between the approximate and the exact outputs as well as the complexity of its design. Also, the presence of some errors in the sum signal will results in a reductions of the delay of pro- ducing the approximate sum and the overall delay of the design (because it is on the critical path). In the last step, the change of the value of c out in some states, may reduce the error distance provided by approximate carry and sum and also more simplification in the proposed design. Although the above mentioned simplifications of carry and sum increase the error rate in the proposed approximate compressor, its design complexity and therefore the power consumption are considerably decreased. This can be realized by comparing (2)-(4) and (5)-(7). Table 2 shows the truth table of the first proposed approximate compressor. It also shows the difference between the inexact output of the proposed approximate compressor and the output of the exact compressor. As shown in Table 2, the proposed design has 12 incorrect outputs out of 32 outputs (thus yielding an error rate of 37.5 percent). This is less than the error rate using the best approximate full-adder cell of [2]. Equations (5)-(7) are the logic expressions for the outputs of the first design of the approximate 4-2 compressor proposed in this manuscript. The gate level structure of the first proposed design (Fig. 6) shows that the critical path of this compressor has still a delay of 3 D , so it is the same as for the exact compressor of Fig. 5. However, the propagation delay through the gates of this design is lower than the one for the exact compressor. For example, the propagation delay in the XOR Ã gate that generates both the XOR and XNOR signals in [8], is higher than the delay through a XNOR gate of the proposed design. Therefore, the critical path delay in the proposed design is lower than in the exact design and moreover, the total number of gates in the proposed design is significantly less than that in the optimized exact compressor of [8]. A second design of an approximate compressor is proposed to further increase performance as well as reducing the error rate. Since the carry and c out outputs have the same weight, the proposed equations for the approximate carry and c out in the previous part can be interchanged. In this new design, carry uses the right hand side of (7) and c out is always equal to c in ; since c in is zero in the first stage, c out and c in will be zero in all stages. So, c in and c out can be ignored in the hardware design. Fig. 7 shows the block diagram of this approximate 4-2 compressor and the expressions below describe its outputs. Note that (9) is the same as (7) and (8) is the same as (6) for c in 1⁄4 0 . Fig. 8 shows the gate level implementation of the second proposed design. The delay of the critical path of this approximate design is 2 D , so it is 1 D ...