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Optical/analog front-end for a TI-ADC-based coherent optical receiver. The optical signal is split into four electrical lanes that are converted by a TI-ADC. PBS: polarization beam splitter; LO: local oscillator; 90 o Hyb: 90 o hybrid coupler.
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This paper introduces a backpropagation-based technique for the calibration of the mismatch errors of time-interleaved analog to digital converters (TI-ADCs). This technique is applicable to digital receivers such as those used in coherent optical communications. The error at the slicer of the receiver is processed using a modified version of the w...
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... the new compensation algorithm proposed in this work can be applied to any high-speed digital communication receiver, to make the discussion more concrete we focus the study on dual-polarization (DP) optical coherent transceivers [1]- [5]. A block diagram of an optical front-end (OFE) for a DP coherent receiver is shown in Fig. 1. The optical input signal is decomposed by the OFE to obtain four components, the in-phase and quadrature (I/Q) components of the two polarizations (H/V). The photodetectors convert the optical signals to photocurrents which are amplified by transimpedance amplifiers (TIAs). The analog front-end (AFE) is in charge of the acquisition ...
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... this section we introduce a discrete-time model for the AFE and TI-ADC system of Fig. 1 including their impairments. A simplified model of the analog path for one component C ∈ {I, Q} in a given polarization P ∈ {H, V } is shown in Fig. 2. Each lane of the AFE includes a filter with impulse response c (P,C) (t) that models the response of the electrical interconnections between the optical demodulator and the TIA, the TIA ...
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... Montecarlo Simulations of the Adaptive CE m ∈ [±0.10]T , respectively, are depicted in Fig. 9, whereas Fig. 10 shows results for 500 random BW mismatches (see (28)) and I/Q time skews (see (29)) uniformly distributed in the ...
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... all cases, it is observed that the proposed compensation technique is able to mitigate the impact of all impairments when they are exercised separately 3 . In particular, notice that the proposed CE with L g = 7 taps practically eliminates the serious impact on the receiver performance of the I/Q time skew values of Table I. Fig. 11 shows histograms of the BER for the receiver with and without the CE in the presence of the combined effects. Results of 500 cases with random gain errors, sampling phase errors, I/Q time skews, BW mismatches, and DC offsets as defined in Table I, are presented. Performance of the CE with L g = 13 taps is also depicted. As before, note ...
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... note that a slight performance improvement can be achieved when the number of taps L g increases from 7 to 13. 3 Similar performance has been verified with random DC offsets [37]. Table I. Figure 11. Histogram of the BER for 500 random cases with combined impairments as defined in Table I. ...
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... k integer, is used to adapt the CE. Fig. 12 depicts an example of the temporal evolution of the BER in the presence of combined impairments according to Table I for different values of the block decimation factor D B with N = 8192. The instantaneous BER is evaluated every 10 5 symbols and then processed by a moving average filter of size 40. Gear shifting is used to accelerate ...
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... performance of the mixed-signal scheme of Section III-C is investigated in typical hierarchical ultra high-speed TI-ADCs such as those used in high speed receivers [42], [43], [46]. This hierarchical TI-ADC architecture organizes the T&H in two or more ranks with a high number of subADCs. Fig. 13 depicts an example with two ranks. Rank 1 includes M 1 switches each of which feeds M 2 T&H stages of Rank 2. Then, M 1 × M 2 ADCs are used to digitize the input signal. Successive approximation register (SAR) ADCs are used for this application due to their power efficiency at the required sampling rate and resolution. This approach ...
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... a hierarchical TI-ADC with M 1 = 16 and M 2 = 8 (i.e., M 1 × M 2 = 128 individual converters) is evaluated. A clock jitter of 100 fs RMS is added to this simulation. Notice that the mixed-signal calibration algorithm adjusts the M 1 sampling phases of the switches in the first rank, and the M 1 × M 2 gains and offsets of the individual sub-ADCs. Fig. 14 shows the temporal evolution of both the BER and the mean signal-to-noise-and-distortion-ratio (SNDR) [42]. A slower convergence than the previous simulation is observed as a result of the larger number of converters (i.e., 128 vs 16). Nevertheless, we verify that the proposed backpropagation based mixed-signal compensation scheme is ...
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... the parallelism factor P can be chosen to be a multiple of the ADC parallelism factor M , i.e., P = q × M where q is an integer. Therefore the different time multiplexed coefficients are used in fixed positions of the parallelism without incurring in significant additional complexity in relation to a filter with just one set of coefficients (see Fig. 15). We highlight that the resulting filter is equivalent in complexity to the I/Q-skew compensation filter already present in current coherent receivers [1]. Since the proposed scheme also corrects skew, the classical skew correction filter can be replaced by the proposed CE without incurring significant additional area or ...
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... the new compensation algorithm proposed in this work can be applied to any high-speed digital communication receiver, to make the discussion more concrete we focus the study on dual-polarization (DP) optical coherent transceivers [1]- [5]. A block diagram of an optical front-end (OFE) for a DP coherent receiver is shown in Fig. 1. The optical input signal is decomposed by the OFE to obtain four components, the in-phase and quadrature (I/Q) components of the two polarizations (H/V). The photodetectors convert the optical signals to photocurrents which are amplified by transimpedance amplifiers (TIAs). The analog front-end (AFE) is in charge of the acquisition ...
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... this section we introduce a discrete-time model for the AFE and TI-ADC system of Fig. 1 including their impairments. A simplified model of the analog path for one component C ∈ {I, Q} in a given polarization P ∈ {H, V } is shown in Fig. 2. Each lane of the AFE includes a filter with impulse response c (P,C) (t) that models the response of the electrical interconnections between the optical demodulator and the TIA, the TIA ...
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... Montecarlo Simulations of the Adaptive CE m ∈ [±0.10]T , respectively, are depicted in Fig. 9, whereas Fig. 10 shows results for 500 random BW mismatches (see (28)) and I/Q time skews (see (29)) uniformly distributed in the ...
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... all cases, it is observed that the proposed compensation technique is able to mitigate the impact of all impairments when they are exercised separately 3 . In particular, notice that the proposed CE with L g = 7 taps practically eliminates the serious impact on the receiver performance of the I/Q time skew values of Table I. Fig. 11 shows histograms of the BER for the receiver with and without the CE in the presence of the combined effects. Results of 500 cases with random gain errors, sampling phase errors, I/Q time skews, BW mismatches, and DC offsets as defined in Table I, are presented. Performance of the CE with L g = 13 taps is also depicted. As before, note ...
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... note that a slight performance improvement can be achieved when the number of taps L g increases from 7 to 13. 3 Similar performance has been verified with random DC offsets [37]. Table I. Figure 11. Histogram of the BER for 500 random cases with combined impairments as defined in Table I. ...
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... k integer, is used to adapt the CE. Fig. 12 depicts an example of the temporal evolution of the BER in the presence of combined impairments according to Table I for different values of the block decimation factor D B with N = 8192. The instantaneous BER is evaluated every 10 5 symbols and then processed by a moving average filter of size 40. Gear shifting is used to accelerate ...
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... performance of the mixed-signal scheme of Section III-C is investigated in typical hierarchical ultra high-speed TI-ADCs such as those used in high speed receivers [42], [43], [46]. This hierarchical TI-ADC architecture organizes the T&H in two or more ranks with a high number of subADCs. Fig. 13 depicts an example with two ranks. Rank 1 includes M 1 switches each of which feeds M 2 T&H stages of Rank 2. Then, M 1 × M 2 ADCs are used to digitize the input signal. Successive approximation register (SAR) ADCs are used for this application due to their power efficiency at the required sampling rate and resolution. This approach ...
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... a hierarchical TI-ADC with M 1 = 16 and M 2 = 8 (i.e., M 1 × M 2 = 128 individual converters) is evaluated. A clock jitter of 100 fs RMS is added to this simulation. Notice that the mixed-signal calibration algorithm adjusts the M 1 sampling phases of the switches in the first rank, and the M 1 × M 2 gains and offsets of the individual sub-ADCs. Fig. 14 shows the temporal evolution of both the BER and the mean signal-to-noise-and-distortion-ratio (SNDR) [42]. A slower convergence than the previous simulation is observed as a result of the larger number of converters (i.e., 128 vs 16). Nevertheless, we verify that the proposed backpropagation based mixed-signal compensation scheme is ...
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... the parallelism factor P can be chosen to be a multiple of the ADC parallelism factor M , i.e., P = q × M where q is an integer. Therefore the different time multiplexed coefficients are used in fixed positions of the parallelism without incurring in significant additional complexity in relation to a filter with just one set of coefficients (see Fig. 15). We highlight that the resulting filter is equivalent in complexity to the I/Q-skew compensation filter already present in current coherent receivers [1]. Since the proposed scheme also corrects skew, the classical skew correction filter can be replaced by the proposed CE without incurring significant additional area or ...
