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The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. LECTOR is a technique for designing CMOS circuits in order to reduce the leakage current without affecting the dynamic power dissipation, which made LECTOR a better technique in leakage power reduct...
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Citations
... Zigzag technique is introduced in 2005. Here, in each logic stage either in NMOS or PMOS one sleep transistor is used in this technique in accordance with the input vector to achieve the lowest possible leakage power consumption [5] but amongst them LECTOR is the most efficient technique because it reduces the leakage current without affecting the dynamic power dissipation [6]. ...
em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em
... In GALEOR approach, one gate leakage high VT NMOS transistor is introduced between the output and the pull up network and another gated leakage high VT PMOS transistor in inserted between output and the pull down network [2][6] as shown in figure 3. Due to the threshold voltage loss caused by high VT MOS transistors, this technique suffers from significant low voltage swing where low logic level appears much above than 0 and high logic level occurs much below than VDD. Increase of propagation delay is result of low output voltage swing [1] [5]. ...
