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Caching recently referenced IP addresses and their forwarding in- formation is an effective strategy to increase routing lookup speed. This paper proposes a multizone non-blocking pipelined cache for IP routing lookup that achieves lower miss rates compared to previously reported IP caches. The two- stage pipeline design provides a half-prefix half...
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... We focus our attention on two key components: the cache and the lookup table. The cache design uses a non-blocking Multizone-Pipelined Cache (MPC) that we first presented in[15]. MPC uses prefix caching in multiple zone caches to improve cache miss ratio. ...
... Improving the cache miss rate through the appropriate usage of prefixes can thus compensate for a large cache miss penalty, and may additionally allow a simple LUT with fast table updates. Alternately, a non-blocking cache could be used, and would hide memory latency by overlapping LUT operations with cache accesses[6,15]. ...
... The multizone pipelined cache (MPC)Fig. 9presents a structural description of our design for a Multizone-Pipelined Cache (MPC)[15]. In the MPC the DAA is divided into two independently sized horizontal parts that form the two zones of the cache. ...
This paper proposes a novel Internet Protocol (IP) packet forwarding architecture for IP routers. This architecture is comprised of a non-blocking Multizone Pipelined Cache (MPC) and of a hardware-supported IP routing lookup method. The paper also describes a method for expansion-free software lookups. The MPC achieves lower miss rates than those reported in the literature. The MPC uses a two-stage pipeline for a half-prefix/half-full address IP cache that results in lower activity than conventional caches. MPC’s updating technique allows the IP routing lookup mechanism to freely decide when and how to issue update requests. The effective miss penalty of the MPC is reduced by using a small non-blocking buffer. This design caches prefixes but requires significantly less expansion of the routing table than conventional prefix caches. The hardware-based IP lookup mechanism uses a Ternary Content Addressable Memory (TCAM) with a novel Hardware-based Longest Prefix Matching (HLPM) method. HLPM has lower signaling activity in order to process short matching prefixes as compared to alternative designs. HLPM has a simple solution to determine the longest matching prefix and requires a single write for table updates.
... Since 2000, most of the research on caching for network routing has been focused on prefix caches [21,3], as well as 'multizone' caches, in which the cache is partitioned into different sections based on the length of the prefixes they store [8,30,25,18]. Here the focus will be solely on methods developed to handle routing prefix dependencies, as these methods are applicable to prefix caching in both the NP model, as well as the distributed model described in Section 1.1.2. ...
... The predominant strategies for dealing with the problem involve either refusing to cache prefixes with dependencies, or alternatively, modifying the routing table to either remove or reduce the number of dependencies [21,3,18]. Before describing the strategies, first consider the example the set of 4-bit routing prefixes in Figure 1.1. In this figure, the routing prefixes are arranged so that child prefixes are dependencies of their parents. ...
Internet routers forward a data packet based on the packet destination IP address. To do this, the routers must find the longest matching prefix with a packet destination address in the routing tables. Increasing the size of the Internet network increases the size of the routing tables that complicate the longest matching prefix problem. Several new approaches have been proposed to accelerate this process. Most proposed algorithms based on binary search algorithms such as a binary trie or a binary search tree, however, the binary trie involves many empty internal nodes. In this paper, a new IP address lookup algorithm using a dynamic content binary trie (DCB-Trie) is proposed. The proposed algorithm is based on the principle of exploitation the empty nodes in the binary trie for storing copies of most recently used prefixes. The results of performance evaluation show that our algorithm is efficient in terms of the lookup speed since search can be immediately finished when the input IP address matches a copy of a leaf prefix in an internal node without arrives to a leaf node.
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Routers are one of the important entities in computer networks specially the Internet. Forwarding IPpackets is a valuable and vital function in Internet routers. Routers extract destination IP addressfrom packets and lookup those addresses in their own routing table. This task is called IP lookup.Internet address lookup is a challenging problem due to the increasingrouting table sizes. TernaryContent-Addressable Memories (TCAMs)are becoming very popular for designing high-throughputaddress lookupengines on routers: they are fast, cost-effective and simple to manage. Despite theTCAMs speed, their high power consumption is their major drawback. In this paper, MultilevelEnabling Technique (MLET), a power efficient TCAM based hardware architecture has beenproposed. This scheme is employed after an Espresso-II minimization algorithm to achieve lowerpower consumption. The performance evaluation of the proposed approach shows that it can saveconsiderable amount of routing table’s power consumption.
