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Normalized drain current variation for three sets of NMOS devices with various finger number and gate length and width belonging to the 65 nm and 90 nm low power processes from foundry A and to the 90 nm process from foundry B. Devices were exposed to a 10 Mrad total ionizing dose of X-rays or -rays.
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This paper is concerned with the study of the total ionizing dose (TID) effects in NMOS transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers. Results from static and noise measurements are used to collect further evidence for a static and noise degradation model involving charge buildup in shallow trench isolations a...
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... normalized current increase was detected in transistors irradi- ated with X-rays. This may be ascribed to the smaller fractional yield of 10 keV X-rays with respect to -rays [15] and/or to a possible enhanced low dose rate sensitivity effect in the edge devices [5], resulting in a larger value of the product in the case of irradiated samples. Fig. 4 shows the normalized drain current variation as a function of for three sets of NMOS transistors with var- ious finger number and gate length and width belonging to the three CMOS processes under test. As in the previous figure, the dashed lines are used to indicate the mean value of the current in each set. Data in Fig. 4 were taken ...
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... of irradiated samples. Fig. 4 shows the normalized drain current variation as a function of for three sets of NMOS transistors with var- ious finger number and gate length and width belonging to the three CMOS processes under test. As in the previous figure, the dashed lines are used to indicate the mean value of the current in each set. Data in Fig. 4 were taken at the same overdrive voltage . The threshold voltage , as well as the subthreshold swing in CMOS processes, are generally adjusted through additional, purpose-made implan- tation steps. Additional dopant species are also implanted to prevent punch through [14]. Changing the doping concentration in the device body should be ...
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... through the CMOS generations and the manufacturers, in the device fabrication techniques and in the material quality). Once the threshold voltage is accounted for, a fair comparison among the three technologies can be performed in terms of radiation-induced drain current change. Note that, at the overdrive voltage of at which the data shown in Fig. 4 were taken, based on the results of Table I, parasitic devices are made to work well over the threshold, as , giving . Although the average values of the three sets of data shown in Fig. 4 are relatively close to each other ( in the 90 GP technology being just a factor of 3 smaller than in the 90 nm LP process), nevertheless 90 nm ...
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... the three technologies can be performed in terms of radiation-induced drain current change. Note that, at the overdrive voltage of at which the data shown in Fig. 4 were taken, based on the results of Table I, parasitic devices are made to work well over the threshold, as , giving . Although the average values of the three sets of data shown in Fig. 4 are relatively close to each other ( in the 90 GP technology being just a factor of 3 smaller than in the 90 nm LP process), nevertheless 90 nm devices from foundry B feature a clear advantage over the LP processes, whose specific fabrication steps might be responsible for the slightly worse performance. These results are consistent ...
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Citations
... Despite this, TID still affects the low-frequency noise of smaller devices, related to interface traps at the Si/SiO 2 interface and border traps in oxide near the interface (2-3 nm). Some studies have focused on the low-frequency noise of MOSFETs under irradiation [7][8][9][10][11][12][13][14][15]. However, most of these studies only compared the low-frequency noise of devices before and after irradiation with a certain dose, and few have studied the degradation trend of the low-frequency noise of devices in a wider range of radiation doses. ...
In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at different irradiation doses and separate the threshold-voltage shifts caused by the oxide-trap charge and interface-trap charge. Moreover, the increased densities of the oxide-trap charge projected to the Si/SiO2 interface and interface-trap charge are calculated. The results of our experiment suggest that the magnitudes of low-frequency noise do not necessarily increase with the increase in border-trap density. A novel physical explanation for the low-frequency noise in SOI-NMOSFETs with high interface-trap density is proposed. We reveal that the presence of high-density interface traps after irradiation has a repressing effect on the generation of low-frequency noise. Furthermore, the exchange of some carriers between border traps and interface traps can cause a decrease in the magnitude of low-frequency noise when the interface-trap density is high.
... As illustrated in Fig. 2.11b, fixed states refer to oxide bulk traps that do not communicate with the substrate, while switching states correspond to border traps and interface traps that exchange charges with the substrate. For MOS devices, fixed states only influence static characteristics through a negative threshold voltage shift, while switching states additionally affect low-frequency noise characteristics [46,156]. ...
... For pMOSFETs, positive interface-trapped charges simply add a negative threshold voltage shift to the negative threshold voltage shift induced by positive oxide-trapped charges. In addition to influencing static characteristics, radiation-activated interface traps, as part of switching states, also degrade low-frequency noise characteristics of MOS devices [46,156,156]. ...
... For pMOSFETs, positive interface-trapped charges simply add a negative threshold voltage shift to the negative threshold voltage shift induced by positive oxide-trapped charges. In addition to influencing static characteristics, radiation-activated interface traps, as part of switching states, also degrade low-frequency noise characteristics of MOS devices [46,156,156]. ...
Total ionizing radiation compromises electrical characteristics of microelectronic devices and even causes functional failures of integrated circuits. It has been identified as a potential threat to electronic components, especially those in high-energy physics experiments, space and avionic systems, and nuclear power plants. Among all harsh radiation environments, the future High Luminosity Large Hadron Collider (HL-LHC) at European Organization for Nuclear Research (CERN), is expected to have by far the highest levels of total ionizing dose (TID) with a peak of 1 Grad in the innermost electronics. Also, the number of pileup events per bunch crossing can reach up to 200, challenging trigger and data acquisition systems of its particle experiments. To reach long-term reliable operation, the HL-LHC will require innovative detecting and tracking systems with a higher level of granularity and bandwidth as well as robust radiation-tolerant front-end electronics.
Complementary metal-oxide-semiconductor (CMOS) scaling allows extended circuit functionality and enhanced computing power. It also improves the TID tolerance of MOS field-effect transistors (MOSFETs) with relieved charge trapping related to ultrascaled gate dielectrics. To evaluate the potential use of highly scaled devices in the HL-LHC and eventually support circuit design for radiation-tolerant applications, this thesis characterizes and models the effects of TID up to 1 Grad on a commercial 28-nm bulk CMOS process. The characterization part focuses on evaluating measurable radiation effects and identifying dominant physical mechanisms. The modeling part aims at improving the understanding of the observed radiation effects and developing a design-oriented compact model for comprehensively accounting for them.
Under various bias and temperature conditions, devices are irradiated, annealed, and tested after each irradiation and annealing step. Most of them demonstrate slight parametric shifts, confirming the very high TID tolerance of ultrathin gate dielectrics. TID-induced degradation in this technology primarily depends on charge trapping related to thick shallow trench isolation (STI) oxides. STI-trapped positive charges in nMOSFETs open parasitic channels along STI sidewalls and cause a significant increase in the drain leakage current, which however almost disappears after high-temperature annealing. STI-related charge trapping can even be strong enough to influence the central part of a narrow channel and is seen seriously degrading the performance of narrow-channel MOSFETs, which however can be relieved by shortening the channel.
The TID-induced parasitic leakage current of nMOSFETs is modeled via a gateless charge-controlled transistor. To model the effects of TID on inversion operation, a generalized Enz-Krummenacher-Vittoz (EKV) charge-based MOSFET model is developed through the incorporation of radiation-induced trapped charges into the original EKV MOSFET model. Despite a small number of parameters, this model demonstrates an excellent match with measurement results over a wide range of device operation. The effects of TID on MOSFET characteristics are efficiently described by those few model parameters. This newly-developed radiation-aware EKV MOSFET model also demonstrates a width dependence of TID effects on 28-nm bulk MOSFETs, which can be explored for the model extension to a broad range of device dimensions even for a continuous range of TID levels.
... In contrast, Fig. 3 shows that core devices still show small effective V th shifts. The large increases in edge leakage are due to radiation-induced trapped positive charge in the STI and buried oxide, as illustrated in Fig. 5, as often observed in SOI technologies [15][16][17][18]. The multi-finger structure used in the RF structures is the most likely origin of the higher radiation-induced edge leakage paths [14,19]. ...
... The thicker gate oxide for the IO devices will lead to a higher tilt angle at the corner of STI and gate oxide, which will enhance radiation-induced charge trapping in the gate edge area, leading to higher leakage during TID [16,18]. Moreover, the lower doping concentration in the IO devices will render these devices more sensitive to TID-induced leakage [15,17]. Fig. 8 shows the IO devices mobility degradation trends and the change in value is less than 5%. ...
... The increased power dissipation associated with the increased STI leakage degrades the forward power gain S 21 significantly, especially for IO devices [23]. Radiation induced traps under the gate and in the gate/drain/STI corner region lead to increased channel resistance and increased device capacitance [15,17,24,25]. This degrades the normalized current gain |h 21 | (Fig. 12). ...
Total-ionizing-dose irradiation-induced RF performance degradation is observed in the input-output (IO) and core transistors of a 130 nm SOI NMOS technology. Different MOS structures including Floating Body(FB), T-gate Body(TB) and Tunnel Diode Body Contact(TDBC) SOI structures, were fabricated in a fully-integrated 130 nm SOI process. The radiation-induced DC and RF response of these devices was investigated. The impact of different structures and the use of body contact at PDSOI on the RF TID behavior are discussed by comparing their results to ionizing radiation experiments.
... This allows two parallel leakage components to flow from drain to source, even when the main nMOSFET is switched off, as shown in Fig. 1. The situation becomes even worse for a multi-finger nMOSFET because the total parasitic drain-to-source leakage current scales with the number of fingers [17], as shown in Fig. 2. This radiation-induced leakage current questions the main advantage of nanoscale CMOS technologies-i.e., low power consumption [18]. ...
... The weak inversion approximation presents almost the same results as the full simplified EKV MOSFET model, except the slight mismatch at ultra-high TID levels where the lateral parasitic n-QFET approaches the moderate inversion. In addition, the straight lines fit the relation of Q 2 oxeq ∝ k ln(TID/TID crit ) in (17). The weak inversion model is therefore a very good approximation for the parallel parasitic drain-to-source leakage current. ...
This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of nMOSFETs fabricated with a commercial
28-nm bulk CMOS process. Experimental comparisons among individual nMOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the
drain leakage current. We introduce a semi-empirical physics-based approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based EKV MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices.
... Figure 4 (left) shows an example of the behavior of the total drain current, before and after exposure to a 10 Mrad total dose of γ-rays, as a function of the gate-to-source voltage for 130 nm and 65 nm NMOSFETs. The plot also shows the current I D,lat (whose value is obtained by subtracting the preirradiation I D from the total drain current measured after irradiation, as explained in [13]) flowing in the lateral parasitic device. The drain current is more severely affected by sidewall leakage in the 130 nm technology as compared to the 65 nm one. ...
A charge preamplifier has been developed in a 65 nm CMOS technology for processing the signals from the inner pixel layers of the CMS detector, in view of the experiment upgrade for the High Luminosity (HL) LHC. The circuit is part of a readout channel implementing a time-over-threshold method for analogto- digital conversion of the input charge signal. Samples of the circuit have been exposed to high doses of ionizing radiation, up to 500 Mrad(SiO2), from a low energy proton source and from an X-ray tube. The test results show that the performance degradation, in terms of charge sensitivity, signal shape and noise is compatible with operation in the harsh environment of the HL-LHC. Measurement data from the characterization of preamplifiers using different kinds of capacitors in the feedback network help gain some insight into the damage mechanisms in PMOS transistors irradiated with large ionizing doses. The dependence of performance degradation on the kind of radiation source used in the tests is also discussed.
A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36°C, the VCO achieves an output power of 0.1 dBm and a phase noise of -99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36°C, 75°C, and 100°C show degradation in frequency, output power, and phase noise. At 100°C and 500 krad(SiO
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), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36°C and up to 500 krad(SiO
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), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification.
Total ionizing dose effects are studied in 130-nm transistors and pixel sensors in a vertically integrated two-layer CMOS technology, evaluating the possible impact of 3D integration on radiation tolerance and damage mechanisms. Measurements of static characteristics and noise voltage spectra before and after exposure to high total ionizing doses demonstrate that the analog performance of transistors as well as their radiation hardness are not degraded by mechanical and thermal stresses occurring during the fabrication of the 3D chips. The paper also presents irradiation results on 3D CMOS pixel sensors with a sparsified readout architecture. After exposure to ionizing radiation, these devices behave in a very similar way as analogous counterparts in a standard 2D 130-nm process, confirming that performance advantages associated with 3D integration are not impaired by an enhanced radiation sensitivity.
