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| Non-volatile memory cell for STeP-CiM showing (A) Schematic illustration, (B) symbol, and (C) layout. (D) Schematic representation of the STeP-CiM cell with an example of biases for write operation (ternary 1). Two-phase write operation depicting in (E) −P → +P polarization switching when V GB = 0.8 V > V C and (F) +P → −P polarization switching when V GB = −0.8 V < −V C . +P and −P states being written to M 1 and M 2 constitute ternary storage of W = +1.
Source publication
We proposed 2D piezoelectric FET (PeFET)–based compute-enabled non-volatile memory for ternary deep neural networks (DNNs). PeFETs hinge on ferroelectricity for bit storage and piezoelectricity for bit sensing, exhibiting inherently amenable features for computation-in-memory of dot products of weights and inputs in the signed ternary regime. PeFET...
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... STeP-CiM cell can be reconfigured to serve as a standard memory (with 2 bit cells) or a compute-enabled memory for ternary precision as per application needs (further discussion on this in Section 6). Using two access transistors (such as AX 1 and RAX 1 in M 1 ) does not lead to any area penalty in the layout shown in Figure 6C. This is because the layout area is dictated by the PeFET footprint arising from the wide PE requirement for hammer and nail effect. ...
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... store ternary "1" in STeP-CiM, +P and −P are written in M 1 and M 2 as per Table 3A. This operation is depicted by Figures 6D-F. First, BL 1 is driven to V DD > V C and BL 2 to 0 V. RBL 1/2 are kept at 0 V. Next, WL is asserted to V DD + V TH (boosted to compensate for threshold voltage V TH drop in write access transistors). ...
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... two-phase signal ( Li et al., 2019) facilitates writing "1" and "0" states to multiple PeFETs as follows. PeFET in M 1 ( Figure 6E) experiences V GB = V BL1 −V CWL = 0.8 V during Φ 1 since V BL1 = 0.8 V and V CWL = 0 V. This results in −P → + P switching. ...
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... results in −P → + P switching. M 2 ( Figure 6F) experiences V GB = V BL2 −V CWL = 0 (as V BL2 = 0 V and V CWL = 0 V) during Φ 1 and the previous polarization state is preserved. During Φ 2 , M 1 retains its state of Φ 1 (V GB = 0) while M 2 switches to −P after receiving V GB = −0.8 ...
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... compare them with near-memory designs based on PeFETs (PeFET-NM) and 2D FET based SRAM (SRAM-NM). The STeP-CiM cell presented in Figure 6A can be readily repurposed for near-memory compute by maintaining CWL = 0 V (akin to PiERRe condition), during these operations. We name this mode as PeFET-NM. ...
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... use these rules in conjunction with Intel defined 20 nm gate/metal pitch rules (Intel 20 nm Lithography). The area of PeFET-NM/STeP-CiM obtained from the layout in Figure 6C is 202.5F 2 while that of SRAM-NM is 378F 2 . We estimate the area of SRAM-NM based on the layout analysis of 2D FET SRAM by (Thakuria et al., 2020). ...
Citations
... However, due to the cross-point connections and the sneak current paths between various cells in the array, these two extreme sweeps may result in different IBL values. In other words, each a is now represented by a range of IBL (IBLMIN to IBLMAX) corresponding to the IN and W sweeps [26], [27]. Therefore, the SM for a given a and a-1 outputs is defined as (IBL,MIN,a -IBL,MAX,a-1)/2. ...
... In our design, we minimize the loading effect by co-optimizing the XNOR-VSH device and array, as will be discussed in the next section. Our results in Fig. 5(b) show that our proposed XNOR-VSH array exhibits a high linearity between IBL and a, and sufficiently large SM (> 1 μA [26]) is obtained. The SM will be compared to other MTJ-based alternatives and discussed shortly in the following section. ...
Binary neural networks (BNNs) have shown an immense promise for resource-constrained edge artificial intelligence (AI) platforms as their binarized weights and inputs can significantly reduce the compute, storage and communication costs. Several works have explored XNOR-based BNNs using SRAMs and nonvolatile memories (NVMs). However, these designs typically need two bit-cells to encode signed weights leading to an area overhead. In this paper, we address this issue by proposing a compact and low power in-memory computing (IMC) of XNOR-based dot products featuring signed weight encoding in a single bit-cell. Our approach utilizes valley-spin Hall (VSH) effect in monolayer tungsten di-selenide to design an XNOR bit-cell (named ‘XNOR-VSH’) with differential storage and access-transistor-less topology. We co-optimize the proposed VSH device and a memory array to enable robust in-memory dot product computations between signed binary inputs and signed binary weights with sense margin (SM) > 1 μA. Our results show that the proposed XNOR-VSH array achieves 4.8% ~ 9.0% and 37% ~ 63% lower IMC latency and energy, respectively, with 49% ~ 64% smaller area compared to spin-transfer-torque (STT)-MRAM and spin-orbit-torque (SOT)-MRAM based XNOR-arrays. We also present the impact of hardware non-idealities and process-variations in XNOR-VSH on system-level accuracy for the trained ResNet-18 BNNs using the CIFAR-10 dataset.
... However, due to the cross-point connections and the sneak current paths between various cells in the array, these two extreme sweeps may result in different IBL values. In other words, each a is now represented by a range of IBL (IBLMIN to IBLMAX) corresponding to the IN and W sweeps [26], [27]. Therefore, the SM for a given a and a-1 outputs is defined as (IBL,MIN,a -IBL,MAX,a-1)/2. ...
... In our design, we minimize the loading effect by co-optimizing the XNOR-VSH device and array, as will be discussed in the next section. Our results in Fig. 5(b) show that our proposed XNOR-VSH array exhibits a high linearity between IBL and a, and sufficiently large SM (> 1 μA [26]) is obtained. The SM will be compared to other MTJ-based alternatives and discussed shortly in the following section. ...
Binary neural networks (BNNs) have shown an immense promise for resource-constrained edge artificial intelligence (AI) platforms as their binarized weights and inputs can significantly reduce the compute, storage and communication costs. Several works have explored XNOR-based BNNs using SRAMs and nonvolatile memories (NVMs). However, these designs typically need two bit-cells to encode signed weights leading to an area overhead. In this paper, we address this issue by proposing a compact and low power in-memory computing (IMC) of XNOR-based dot products featuring signed weight encoding in a single bit-cell. Our approach utilizes valley-spin Hall (VSH) effect in monolayer tungsten di-selenide to design an XNOR bit-cell (named 'XNOR-VSH') with differential storage and access-transistor-less topology. We co-optimize the proposed VSH device and a memory array to enable robust in-memory dot product computations between signed binary inputs and signed binary weights with sense margin (SM) > 1 micro-amps. Our results show that the proposed XNOR-VSH array achieves 4.8% ~ 9.0% and 37% ~ 63% lower IMC latency and energy, respectively, with 4 % ~ 64% smaller area compared to spin-transfer-torque (STT)-MRAM and spin-orbit-torque (SOT)-MRAM based XNOR-arrays.
