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In this work, we report a single-voltage-supply-operated current-reused complementary 3.7–11.9 GHz CMOS low-noise amplifier (LNA) for sub-6 GHz 5G systems. The body-floating and self-forward-bias technique, i.e., the body of the transistor is connected to its drain through a large resistance (7.7 or 11.5 k Ω\documentclass[12pt]{minimal} \usepackage...
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Citations
... Figure 23 Table 2 summarizes the performance metrics of recently published UWB LNAs using standard 0.18 µm CMOS nodes. The figure of merit (FOM) can be expressed as [6,16,22]: ...
This study presents a wideband low-noise amplifier (LNA) chip that covers the frequency range of 2.8–10 GHz using UMC’s 0.18 μm complementary metal–oxide–semiconductor technology. The LNA adopts a current reuse architecture to reduce power consumption. This study improves linearity using multiple gated transistors and inductance degeneration techniques. In addition to enhancing linearity, the proposed technique also achieves high gain and broadband. The DC power dissipation of this LNA was 18 mW with a 1.5 V supply voltage. The measured minimum noise figure was 4.5 dB. Furthermore, the gain, input third-order intercept point, and total chip size of the LNA were 10.8–13.8 dB, 2 dBm, and 1.18 × 1.19 mm², respectively. The proposed LNA measurements exhibit high linearity, high gain, an optimal reflection coefficient, and a low supply voltage.
... The input impedance matching of this structure is realized with resistive feedback, but due to the parasitic capacitors of the transistor, this impedance matching does not occur over the entire frequency range of the LNA. To solve this problem, an inductor can be placed in the structure [4,13,14,16,19] to maintain good impedance matching over the entire frequency band of the amplifier as well as out-of-band filtering. Numerous articles on nonlinear improvement and noise cancelation of this structure are also proposed [5,7,10]. ...
In order to improve the out-of-band interference filtering in the front-end of a wideband radio frequency system, this paper proposes a two-stage low-noise amplifier (LNA) that has three notches in its transfer function. In the proposed LNA, two center-tap inductors are utilized, where the center-tap inductor is modeled as two equal inductors with a mutual coupling. Here, by properly designing these two inductors and their coupling, in the utilized two center-tap inductors, three notches and proper peaking in the transfer function of the LNA, as well as input matching, are simultaneously realized. The proposed LNA is fabricated in 65 nm CMOS, and its active area is 0.13 mm2. The LNA shows three notches at 2.9 GHz, 13.1 GHz and 17.2 GHz. Moreover, the 3 dB BW is from 5.4 GHz to 8.7 GHz, sufficiently wide to operate in the worldwide ultra-wideband (UWB) regulated spectrum. The proposed LNA power consumption is 9.9 mW from a 1.1 V supply, with a minimum noise figure of 3.4 dB and a gain of 24.8 dB.
... However, its bandwidth is limited without the use of the inductor components [12,13]. The resistive shunt feedback amplifier can improve gain flatness and provide wideband input impedance matching, but it is difficult to satisfy noise figure and voltage gain requirements simultaneously [14,15]. ...
In this paper, an inductorless and gain-controllable 0.5~2.5 GHz wideband low noise amplifier (LNA) based on second generation current controlled current conveyors (CCCIIs) is presented. The proposed wideband LNA utilizes CCCIIs as building blocks to implement the amplifier stage and impedance matching stage. By varying the DC biasing current of the CCCII, the voltage gain of the proposed LNA is controllable in the range of 1~18 dB. In the frequency range of 0.5~2.5 GHz, the post-layout simulation results show that the proposed LNA has a typical voltage gain S21 of 12.6 dB with a gain ripple of 1.5 dB, an input and output return loss (S11 and S22) of, respectively, −21.4 dB to −16.6 dB and −18.6 dB to −10.6 dB, and a high reverse isolation S12 of −65.2 dB to −39.5 dB. A noise figure of 4.05~4.35 dB is obtained across the whole band, and the input third-order intercept point (IIP3) is −2.5 dBm at 1.5 GHz. Using a 0.18 μm RF CMOS technology, the LNA occupies an active chip area of only 0.096 mm2 with a power consumption of 12.0 mW.
