Figure 6 - uploaded by Emmanuel Augendre
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NMOS gate to junction leakage current at V drain = 1.2V (V gate = V source = V well = 0). The comparison is for 150nm poly silicon gate electrode thickness versus 100nm poly silicon gate electrode thickness and different sidewall oxidation recipes. Each marker represents an average of at least 20 measurements for a given gate length.
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... SRAM cells consisting of 2 nFETs and 2 pFETs ( Fig. 1) with L = 0.13 µm and 1.7 nm EOT (NCSU) were fabricated using the process described in Ref. [9]. Pass gates were not included in the SRAM design for simplicity. ...
The effect of hard and soft gate oxide breakdown on SRAM cells is investigated experimentally. SRAM cells based on two FET widths are used. We demonstrate that while SRAM cells with wide gates can retain information even after a hard breakdown, SRAM cells with more typical, narrow gates fail after a hard breakdown of the same magnitude. This is because the narrow FETs cannot compensate the additional current flowing through the hard breakdown path. However, both types of SRAM cells can retain information after their gate oxide undergoes soft breakdown. Soft breakdown is the expected mode of gate oxide failure at operating conditions in present and upcoming CMOS technologies.
Simple analytical expressions are presented, which calculate the impact of line edge roughness on MOSFET parameter fluctuations. It is experimentally demonstrated that LER has no impact on 80 nm gate length transistors. Simulations show LER to become significant for 32 nm channel length devices.
