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The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS)technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-techelectronics industries from consumer products to telecommunications and computers. As CMOStechnologies are scaled down into the nanometer range, a...
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... typical schematic structure of CMOS transistor is given in fig. 1. In conventional NMOS circuit, Figure 1 (a), the substrate is normally connected to ground or lowest potential in the circuit and in PMOS circuits, the substrate is connected to supply voltage or the highest potential in the circuit [9]. Over the past decades, CMOS technology scaling has been a primary driver of the electronics ...
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... typical schematic structure of CMOS transistor is given in fig. 1. In conventional NMOS circuit, Figure 1 (a), the substrate is normally connected to ground or lowest potential in the circuit and in PMOS circuits, the substrate is connected to supply voltage or the highest potential in the circuit [9]. Over the past decades, CMOS technology scaling has been a primary driver of the electronics industry and has provided a denser and faster integration [1-3-10]. ...
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... to inject the resistive path 1 we must use two fault injection transistors (FIT 1 and FIT 2 ) as shown in fig. 12 fig .13, we can notice that when the Op amp is fault free (Defect-injection=0) the output of the BICS is Pass, thus we are sure that the circuit under test does not contains a resistive path between V DD and the ground. On the other side, the injection of the resistive path (Defect- injection=1) change the circuit under test output ...
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... to inject the resistive path 1 we must use two fault injection transistors (FIT 1 and FIT 2 ) as shown in fig. 12 fig .13, we can notice that when the Op amp is fault free (Defect-injection=0) the output of the BICS is Pass, thus we are sure that the circuit under test does not contains a resistive path between V DD and the ground. ...
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The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS)technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nano meter range...
Citations
... Unfortunately, ICs designed in advanced nanoscale technologies exhibit a high sensitivity to significant process parameter variations. Therefore, in these technologies, it is rather difficult to design high performance integrated circuits using standard design techniques and approaches [1], [2]. ...
... Depending on the used converting network, the different network resolution can be achieved, since it is given by the number of bits and weight type of the converting net-work. Using the redundance R, the resolution can be expressed by (2). ...
In this article, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved.
... In many cases the failure analysis of a faulty circuit in the manufacturing test returns negative results, the primary cause for this result is that the test is incomplete because the defect coverage is too low, and thus the manufacturing test cannot identify the faulty parts. The adoption of design for test methods such as scan test and automatic test pattern generators (ATPG) targeted at the stuck-at fault model was the solution to improve the defect coverage (Karmani, Khedhiri, & Hamdi, 2011a). Another popular technique for detection of defects in CMOS VLSI circuits is the I DDQ testing. ...
Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.
... Advanced technologies enable ultra large scale integration and therefore, increase the probabil- ity of presence of physical defects. Furthermore, nanoscale technologies also induce new failure mechanisms such as electromigration, hot-carrier injection, leakage current, etc. [1], [2]. ...
Research presented in this paper is aimed at the comparison of the Oscillation-based Built-In Self Test (OBIST) efficiency in covering catastrophic and parametric faults in active analog integrated filters designed in two different technologies. Sallen-Key topologies of low-pass and high-pass filters were used as Circuit Under Test (CUT), designed in 0.35μm and 90nm CMOS technologies. The presented oscillation test strategy uses the on-chip Schmitt oscillator as the reference frequency source to compensate the influence of process parameter variations. Achieved results show that the proposed BIST approach is fully implementable in nanoscale technologies. Finally, dependence of the fault coverage on the oscillation frequency value was investigated.
... The constant advances in VLSI technology have given the capability to design and manufacture very complex integrated circuits that include digital, analog and mixed circuits in the same chip. The approach based on integrating all these components into a single chip is known as the system-on-a chip (SoC) approach design [1][2]. Although this approach simplifies the design phase of the product, it increases the complexity of testing of the system, in particular testing of the analog blocks or analog functions embedded in mixed-signal or analog cores [2]. ...
... The approach based on integrating all these components into a single chip is known as the system-on-a chip (SoC) approach design [1][2]. Although this approach simplifies the design phase of the product, it increases the complexity of testing of the system, in particular testing of the analog blocks or analog functions embedded in mixed-signal or analog cores [2]. ...
... For CMOS technologies which are of the micro-meter order, a single short between two nodes in the circuit can increase significantly the I DDQ current. Thus, the BICS can easily detect the presence of the fault [2][3][4][5][6][7][8][9]. However in [2] the authors show that at the nano-meter range (90 nm and below) the I DDQ testing is used to diagnose only the multiple bridging faults being able to create a resistive path between V DD and ground. ...
With the continuous increase of integration densities and complexities, secure integrated circuits (ICs) are more and more required to guarantee reliability for safety-critical applications in the presence of soft and hard faults. Thus, testing has become a real challenge for enhancing the reliability of safety-critical systems. This paper presents a Self-Test and Self-Repair approach which can be used to tolerate the most likely defects of bridging type that create a resistive path between VDD supply voltage and the ground occurring in analog CMOS circuits during the manufacturing process. The proposed testing approach is designed using the 65 nm CMOS technology. We then used an operational amplifier (OPA) to validate the technique and correlate it with post layout simulation results.
... The evolutionary trend in very large scale integrated (VLSI) circuits technology fuelled by fierce industrial competition to reduce integrated circuits cost and time to market has driven to design and manufacture very complex ICs including digital, analog and mixed parts in the same chip, this approach is known as system-on-chip (SoC). Due to the increasing complexity and chip scale of SoCs, design and testing have become a real challenge to ensure the functionality and quality of the product12. The SoC design approach increases the testing complexity of the system, in particular testing of the analog blocks embedded in mixed-signal or analog cores [3]. ...
... Usually, bridging faults induce an elevated I DDQ current. Consequently these faults can be easily detected using a Built In Current Sensor (BICS)123456789. On the other side, open circuit faults, may decrease or cause only a small rise in I DDQ current that can not be detected by the built in current sensor. ...
... Thus, when the value of the I DDQ current is 0.5 mA we assume that there are no short-circuit defects, but it is not guaranteed that the circuit don't contain open-circuit defects. When the gate of the fault injection transistor is connected to V DD , the FIT is activated and consequently the fault is injected [1].Figure 10 shows the I DDQ current waveform in presence of the bridging fault. We can notice the increase of the I DDQ current that was sensitive to the fault injected between the source and gate of the transistor M 5 . ...
In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS) analog integrated circuits (ICs) interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre's frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary. In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 µm technology and the most likely faults of open-circuit type are deliberately injected and simulated at the layout level.
... In this work, we focus on the problem of automatic test generation, which involves computing a set of input patterns that permit detecting a given fault (for example, by comparing the differences in the outputs with some predetermined tolerance thresholds). Test generation has been considered for analog circuits such as in [13], [25], [20], for mixed-signal circuits such as in [2], [15], [14], [29],[30], using a variety of techniques, such as static test generation [23],[28], sensitivity computation [13], Monte-Carlo simulation [25], [26], and optimization [5]. Following the model-based design approach, we propose a new test generation method for analog and mixed-signal circuits using hybrid system models. ...
In this paper we propose an approach for testing time-domain properties of analog and mixed-signal circuits. The approach is based on an adaptation of a recently developed test generation technique for hybrid systems and a new concept of coverage for such systems. The approach is illustrated by its application to some benchmark circuits.
Circuit designers are always faced with new obstacles as a result of the persistent trend in today's nanoscale technology to follow Moore's law. The complexities inherent in the production process have increased dramatically due to the rapid downscaling of integration. Parallel to this, the complexity and unpredictability of silicon chip flaws have increased, making circuit testing and diagnosis more challenging. The amount of test data has multiplied, and the criteria governing integrated circuit testing have grown both in size and in the complexity of correlation. The modern situation provides a useful framework for investigating novel machine learning-based test solutions. In this paper, the authors examine different recent developments in this developing field in the context of digital logic testing and diagnosis.
Integrated circuits (ICs) design plays a significant role in the embedded-system performance , reliability and security. Thus, the constant advances in very large-scale integration technology have led to design and manufacture of very complex ICs based on the System on a Chip (SoC) approach design. Therefore, the embedded system testing is considered earlier during the design process and testability is used as one of the objectives for evaluating safety-critical embedded system designs. On the other hand, embedded systems used in critical applications execute security-critical commands and collect sensitive data protected by cryptographic keys and authentication codes. The data and the unauthorised access of these embedded devices is an obvious target for attackers in order to obtain control or extract internal data. In this paper we consider that by using Design for Testability (DFT) approaches an attacker can control and affect a security-critical embedded system. Thus, the authors focus on the DFT approach, as a means of violation of the security and confidentiality of embedded systems with security-critical goals. In addition, with or without insertion of DFT circuitry, the crypto-core is always exposed to the powerful differential fault analysis (DFA) attack. Here, a 32-bit AES crypto-core is used as a case study in order to analyse the DFA-and the DFT-based Hacking techniques. A countermeasure was performed in order to avoid any scan or even DFA attack attempt.
With the prevalence of VLSI technology and electronics devices becoming smaller, denser, smarter and long lasting, the research in the field of low voltage applicability and low power consumption is turning omnidirectional among which one direction leads towards the depth of faster and precise clock generation which is achieved on the foundation of PLL. The time has come to break one of the famous Silicon Valley golden rules which states " Higher the clock frequency, Greater the power consumption ". Keeping the trivial relationship between power consumption and power dissipation in mind, lowering supply voltages is the most effective method to reduce power consumption. At lower supply voltage, it is challenging to optimize each block of PLL for Low Voltage operations. A Low voltage High Frequency ALF Charge Pump PLL is proposed. It employs a differential Charge pump with an active loop filter to compensate current mismatch and reduces reference spurs. A Voltage Controlled Oscillator is designed with body bias technique providing wide capture range and low power consumption. A D Flip Flop PFD is designed with TSPC dynamic logic to achieve zero or minimum dead zone and is able to detect large phase and frequency difference.
