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INLk estimation, α = 1%, 100 ppm drifting. From Figure 3 and Figure 4, we can see that the INL k estimation error has a " bell " shape and the maximum error happens at the middle of the ADC input range. The maximum is inversely proportional to offset α, reduced by half when α is doubled. Further calculation based on (24)
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This work describes a linearity test strategy for ADCs that uses stimuli with precision much lower than the ADC resolution and tolerates environment nonstationarity. This approach can be applied to testing ADCs of very high performance, such as 16-bit or higher resolutions and more than 1 MSPS sampling rates, to which there is hardly a well-establi...
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... INL k estimation results using the SEIR method for a same ADC are plotted in Figure 3 and 4, for offset values as 0.5% and 1% of the total ADC input range, respectively. From Figure 3 and Figure 4, we can see that the INL k estimation error has a "bell" shape and the maximum error happens at the middle of the ADC input range. The maximum is inversely proportional to offset α, reduced by half when α is doubled. ...
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Citations
... In [7] the non-linearity inserted by the stimulus is identified and removed (SEIR) exciting the ADC with two identical non-linear ramps with a voltage offset between them. [8] includes modifications for a test environment where time drifts are not negligible. In [10] the authors introduce a simple and general algorithm based on SEIR but independent of the test signal waveform and adapted to a nonstationary test set-up. ...
This paper reports the testing results of a Successive- Approximation-Register (SAR) ADC of 18-bits with Serial Input/Output digital interface. We compare the results of using a standard approach with a new test methodology for SAR static linearity testing. The available test time in between radiation steps is limited in order to avoid annealing. The presented method strongly reduces the amount of output code samples, which implies not only higher test speed but also lower test cost.
... In [29] and [30] the authors introduce a method for ADC linearity test which permits using signal generators that may be significantly less linear than the device under test. ...
... The ramp will be slow at the positions of the codes we intend to measure and will be very fast at the positions of the codes we do not intend to measure. Furthermore, the Stimulus Error Identification and Removal techniques [29,30] could be incorported to circumvent the inability to obtain a suitable linearity of the stimulus. ...
Differential Non Linearity (DNL) and Integral Non Linearity (INL) are the two main static performances ofAnalog to-Digital Converters (ADCs) typically measured during production testing. These two performances reflect thedeviation of the transfer curve of the ADC from its ideal form. In a classic testing scheme, a saturated sine-wave or ramp isapplied to the ADC and the number of occurrences of each code is obtained to construct the histogram from which DNL andINL can be readily calculated. This standard approach requires the collection of a large volume of data because each codeneeds to be traversed many times to average noise. Furthermore, the volume of data increases exponentially with theresolution of the ADC under test. According to recently published data, testing the mixed-signal functions (e.g. dataconverters and phase locked loops) of a System-on-Chip (SoC) contributes to more than 30% of the total test time, althoughmixed-signal circuits occupy a small fraction of the SoC area that typically does not exceed 5%. Thus, reducing test time forADCs is an area of industry focus and innovation. Pipeline ADCs offer a good compromise between speed, resolution, andpower consumption. They are well-suited for a variety of applications and are typically present in SoCs intended for videoapplications. By virtue of their operation, pipeline ADCs have groups of output codes which have the same width. Thus,instead of considering all the codes in the testing procedure, we can consider measuring only one code out of each group,thus reducing significantly the static test time. In this work, a technique for efficiently applying reduced code testing onpipeline ADCs is proposed. It exploits two main properties of the pipeline ADC architecture and allows obtaining an accurateestimation of the static performances. The technique is validated on an experimental 11-bit, 55nm pipeline ADC fromSTMicroelectronics, resulting in estimated DNL and INL that are practically indistinguishable from DNL and INL that areobtained with the standard histogram technique, while measuring only 6% of the codes.
... Une méthode, proposée par Parthasarathy et al. [101,102], permet d'utiliser un signal de test d'une résolution inférieure au circuit sous test. Cette technique repose sur l'hypothèse selon laquelle les tensions de transition des codes d'un convertisseur de signal sont invariantes. ...
The pervasiveness of the semiconductor industry in an increasing range of applications that span human activity stems from our ability to integrate more and more functionalities onto a small silicon area. The competitiveness in this industry, apart from product originality, is mainly defined by the manufacturing cost, as well as the product reliability. Therefore, finding a trade-off between these two often contradictory objectives is a major concern and calls for efficient test solutions. The focus nowadays is mainly on Analog and Mixed-Signal (AMS) circuits since the associated testing cost can amount up to 70% of the overall manufacturing cost despite that AMS circuits typically occupy no more than 20% of the die area. To this end, there are intensified efforts by the industry to develop more economical test solutions without sacrificing product quality. Design-for-Test (DfT) is a promising alternative to the standard test techniques. It consists of integrating during the development phase of the chip extra on-chip circuitry aiming to facilitate testing or even enable a built-in self-test (BIST). However, the adoption of a DFT technique requires a prior evaluation of its capability to distinguish the functional circuits from the defective ones. In this thesis, we present a novel methodology for estimating the quality of a DfT technique that is readily incorporated in the design flow of AMS circuits. Based on the generation of a large synthetic sample of circuits that takes into account the impact of the process ariations on the performances and test measurements, this methodology computes test metrics that determine whether the DFT technique is capable of rejecting defective devices while passing functional devices. In addition, the thesis proposes a novel, purely digital BIST technique for Sigma-Delta analog-to-digital converters. The efficiency of the test metrics evaluation methodology is demonstrated on this novel BIST technique. Finally, a hardware prototype developed on an FPGA shows the possibility of adapting the BIST technique within a calibration system.
... Les blocs de détection d'INL et DNL sont constituées de portes logique, donc le surcoût en surface est très petit. [9] prouvent qu'il est possible, en appliquant à l'entrée du convertisseur deux signaux non-linéaires, l'un décalé par rapport à l'autre, de remonter aux non-linéarités du convertisseur. L'algorithme utilisé exploite l'information redondante de données obtenues en appliquant les deux signaux, et en identifiant les niveaux du signal correspondants aux mêmes niveaux de transition de l'ADC, un ensemble d'équations n'impliquant que les erreurs du stimulus peuvent être obtenues. ...
Résumé Dans ce papier on va présenter les résultats d'évaluation d'une méthode de test pour les convertisseurs analogique-numérique de type pipeline. La technique consiste à mesurer quelques codes spécifiques permettant de retrouver les caractéristiques de tous les codes du convertisseur. L'évaluation est effectuée sur un design industriel de STMicroelectronics. Les résultats de simulation montrent que les grandes erreurs de linéarité dans le convertisseur sous-test ne sont pas détectées. Une amélioration de la technique peut être envisagée pour une éventuelle utilisation dans un test de production industriel.
... The authors developed a stimulus error identification and removal (SEIR) algorithm to test linearity of high-resolution ADCs using two nonlinear signals [5], and a strategy that minimizes the effect of environment nonstationarity on the test results [6]. The combination of the two methods provides a solution to testing high-performance ADCs utilizing low-linearity stimuli in a realistic time-varying environment. ...
... So the difference between the corresponding estimated values of them should be a constant as well with some estimation error effects. Plugging (8.b) into (6) gives . ...
High-precision analog-to-digital converter (ADC) testing is a challenging problem because of its stringent requirement on a test signal's linearity. This paper introduces a method that uses a nonlinear stimulus signal to test the linearity of high-resolution pipelined and cyclic ADCs by exploiting their architecture property. Simulation and experiments show that 16-bit ADCs can be tested to 1-LSB accuracy by using a 7-bit linear signal. This approach provides a solution to both the production and on-chip testing problems of high-resolution ADCs.
... In the past years, some published works have dealt with decreasing the cost and requirement of the accurate analogue input stimulus for ADC testing. In the work [4][5][6], the authors used two low-resolution ramp signals with offset to test the high-resolution ADC. By applying a stimulus error identification and removal algorithm (SEIR), a 16-bit ADC can be accurately tested by a 7-bit ramp signal. ...
In this paper, two improved methods are presented extending our previous work. The first one improves the results by adjusting the voltage levels of the input pulse wave stimulus. Compared with the sine wave input stimulus, the four-level pulse wave can detect even more faulty cases with the offset faults. The second one improves the results by calculating the similarity of the output spectra between the golden devices and the DUTs. Compared with the previous method [10], it is less sensitive to the jitter and the change of the rise/fall time of the input pulse wave stimulus. In these two methods, a number of golden devices are tested at first to obtain the fault-free range. At last, a signature result is obtained from both methods. It can filter out the faulty devices in a quick way before testing the specific values of the conventional dynamic and static parameters.
... However, the generated waveform is quite dependent on process variations. The references [8] [9] [10] are continuous works with regard to the usage of two imperfect ramp signals with constant offset to test a high resolution ADC. A stimulus error identification and removal (SEIR) algorithm [8] [9] [10] is described for relaxing the linearity requirement of the test signal. ...
... The references [8] [9] [10] are continuous works with regard to the usage of two imperfect ramp signals with constant offset to test a high resolution ADC. A stimulus error identification and removal (SEIR) algorithm [8] [9] [10] is described for relaxing the linearity requirement of the test signal. ...
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow sufficient time for converter settling, is taken as the test stimulus reliving the burden placed on accuracy requirement of excitation source. The objective of the test scheme is not to completely replace traditional specification-based tests, but to provide a reliable method for early identification of excessive parameter variations in production test that allows quickly discarding of most of the faulty circuits before going through the conventional test. The efficiency of the methods is validated on a 6-bit flash ADC.
... In a previous paper, the authors introduced an ADC test algorithm that uses nonlinear signals with stimulus error identification and removal (SEIR) [2]. The authors also developed a signal generation strategy that can eliminate the effect of environment nonstationarity on the test results [3]. The combination of the two methods will provide a solution to production tests of highperformance ADCs, utilizing low-linearity stimuli in a nonstationary environment. ...
This paper describes an approach for analog-to-digital converter (ADC) linearity testing that can tolerate environmental nonstationarity and use low-precision test signals. The effects of stimulus errors on ADC testing results will be identified and removed by exploiting the functional relationship of input signals. The effects of environmental nonstationarity will be suppressed by interleaving input signals with a center-symmetric pattern. This approach can be applied to testing of ADCs of very high performance, such as 16-bit or higher resolution and more than 1 MSPS sampling rates, to which there is hardly a well-established solution for full-code testing. Simulation and experimental results show that a 16-bit ADC can be tested to one-least-significant-bit accuracy by using input signals of seven-bit linearity in an environment with more than 100-ppm/min nonstationarity. The proposed method can help control the cost of ADC production tests, extend the test coverage of current solutions, and enable built-in self-tests and test-based self-calibrations.
This paper seeks to simplify the scope of on-chip built-in self-test (BIST) schemes for the static testing of analog-to-digital converters (ADCs) by relaxing the precision and constancy requirements for the reference voltage of the system. The proposed testing methodology is based on appropriate modifications to the ’Stimulus Error Identification and Removal (SEIR)’ algorithm 1, which already addresses the stringent linearity constraints on the input stimulus. Simulation results with the proposed algorithm are presented for a prototype 14-bit SAR ADC; wherein the non-linearities of the input signal and the non-stationarities of the reference voltages are estimated to obtain the actual ADC performance. Once the ADC linearity is known, standard digital calibration schemes can be employed to achieve higher resolution.
