Model for current leakage caused by surface charge. 

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... MEMS pressure sensor was one of the first silicon sensors developed since the 1950s and is being used in numerous applications all around us [1]. Historically, it is known in the industry that MEMS pressure sensors are sensitive to applied charge on the surface [2, 3]. Surface charge-induced current leakage is shown in a simple model in figure 1. The net negative charge on the passivation surface between the p+ regions creates an inversion channel that allows current leakage between the two p+ implanted regions. This is a known problem, and any manufacturing excursion (wafer fab process, shipping, assembly process) can induce a significant amount of charge before protection (typically gel) is applied. Also depending on the application, the sensor can be exposed to harsh environments that can apply charge on the pressure sensor surface [4]. This is why it is a common practice to cover the sensor surface with a thick ( ∼ 100 μ m) protective gel [5]. Once the protective gel is applied, which is an order of magnitude thicker than the passivation, the applied charge is far enough from the substrate, and the inversion channel cannot be created easily. This case is shown in figure 2. A piezoresistive pressure sensor layout is shown in figure 3. It follows a typical design used in the industry and is currently in production at Freescale (MPL115A) [6]. Metal traces from the metal bond pads contact on the p+ implants. The p+ implants then connect the electrical signal to the sensitive p − implants. Therefore, if there is an inversion channel between the p+ traces that leaks current, the offset value from the Wheatstone bridge can change without mechanical input creating failure during trim coding. Current leakage can create either positive or negative offset changes and either case would cause an error in trim coding. However, offset shift failures in general cannot always be solely explained by charge-induced failure. Mechanical stress from the die attachment or mold stress from the surrounding mold can induce offset shift in the sensing element [7]. Once failure is found during trim code due to high offset, it is critical to find the true root cause of the failure. There can be single or multiple causes of offset shifts and these can be categorized as mainly mechanical failure or electrical failure. Electrical failure is explained by the charge, but mechanical failure can be explained by several factors. These are factors such as package stress from the substrate, from the cap when the gel is touching the lid, wires inducing stress on the sensor. Mechanical factors therefore need to be examined physically by cross section analysis and x-ray analysis. It is very confusing since the symptoms from mechanically induced failures are similar to their electrical counterpart. The trim coding fails during test post assembly, and after thermal stress has been applied or after a long time has elapsed, the failure recovers. This is because both electrical charge and mechanically induced charge can be dispersed or relieved with time and temperature. In this study, we examine two convenient methods to extract the electrical contribution indirectly, so that each root cause can be quantified and removed systematically. In the following the underlying theoretical concepts are summarized to illustrate our extraction technique for determining the surface charge. In order to investigate the effects of charges a method has been developed to artificially apply charges to the sample, which is described in section 3. The analysis of the charge density is performed in section 4 using two different methods. The first relies on numerical 3D simulation of the full geometry of the resistor structure in the presence of charges to reproduce the experimentally observed leakage contributions to the resistor current (section 4.1), while the second approach leverages the physics of the underlying parasitic MOSFET (section 4.2). Findings are summarized in section 5. The parasitic FET current contribution to the resistor current can be described in terms of well-known MOSFET theory [8]. Here, p-type regions of the resistor branches may act as source and drain terminals of the parasitic PMOS device. For a given drain-to-source voltage V ds , applicable carrier mobility μ , inversion layer charge Q inv , device width W and channel length L , the linear model current is given by I FET μ V ds Q inversion μ V ds (Q surface + Q depletion ). L L (1) In a regular MOSFET, the inversion layer charge is determined by the difference between gate and threshold voltage. Here, the field across the insulator is determined by the surface charge Q surface , which is mirrored by the sum of inversion layer and depletion region charge on the silicon side: Q surface = − (Q inversion + Q depletion ). (2) Within the full depletion approximation, the depletion charge can be expressed as Q depletion (V bs ) = 2 ε s qN D ( 2 F + V bs ), (3) where ε s is the silicon dielectric constant, q is the elementary charge, N D is the concentration of donors in the substrate and F is the bulk equilibrium Fermi potential for holes. For increasing surface charge, a depletion region forms at the surface exposing the positive charge of the donors. Once the surface potential has reached a level of 2 F + V bs , a further increase of surface charge induces increasing charge in an inversion layer that forms a conductive channel between p- type regions at the silicon–insulator interface. The depletion charge is a function of the back-gate-to-source voltage V bs , which directly corresponds to the well-known back-gate effect leading to a shift in the MOSFET threshold voltage. As can be seen from substituting equation (3) into equation (1), an increase of the back-gate bias can suppress the parasitic FET current by compensating the entire negative surface charge, thus eliminating available mobile holes in the inversion layer. Therefore, the surface charge can be extracted from determining the threshold back-gate bias V bs , 0 , sufficient to suppress the inversion layer, and consequently, suppressing the parasitic FET leakage current: Q surface = − Q depletion (V bs , 0 ) = − 2 ε s qN D ( 2 F + V bs , 0 ). (4) Since the voltage range that can be applied to the substrate may be limited, and as a consistency test of the findings, it is sometimes convenient to extract the surface charge from the intersection V bs , 1 of the I FET − V bs curve with the substrate voltage axis for vanishing substrate ...