Memory hierarchy design 

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... I NTRODUCTION T oday microprocessors progress and causes development increasing of used technologies gap between in processors and memories speed. This matter necessitates hierarchical memories design with different sizes and speeds for each memory level. Fig. 1 demonstrates a simple memory hierarchy design. A lot of researches have been done on measuring and recommending near optimal cache configurations from a power consumption point of view. The growing demand for embedded computing platforms, mobile systems, general- purpose handheld devices encourages us to work more on the cache performance [13]. For instance, in [1], the authors determined that high performance caches were also the lowest power consuming caches since they reduce the traffic to the lower level of the memory system. In this process parameters like block size, number of sets and replacement algorithms are very effective in increasing accesses to memories. Using improper and inefficient replacement policies in cache structures causes increasing miss rates and therefore increasing access time to a desired block and power consumption too. Therefore selection of an efficient replacement policy has a key role in decreasing hit time and power consumption in memories. Many algorithms can be driven by the use of caches for memory pages in Operating System (OS) implementations, which have different access characteristics than the canonical problems and share many of the same principles [2][15]. Existing cache replacement algorithms do not differentiate between instruction cache and data cache blocks. But it is known that there is a very important difference: Instructions usually are not modified. This fact guides us in developing distinct algorithms with their special features for each of the data and instruction caches. Most of the tools for calculation of power consumption couldn't support our new replacement policies easily. Therefore we decided to modify one of the available simulation tools namely SimpleScalar [3] and added a power support section to it in order to be able to simulate the algorithms. SimpleScalar is an execution-driven simulator that uses binaries compiled to a MIPS-like target. SimpleScalar can accurately model a high-performance, dynamically-scheduled and multi-issue processor. The rest of this paper is organized as follows. Section II studies some existing cache replacement policies that are used in modern systems. Section III proposes three new modified replacement policies and describes them thoroughly. Section IV describes our power formulation in our modified power tool. In section V we evaluate our proposed replacement policies and compare them with the previous implemented algorithms in this tool and analyze the results. Finally, Section VI summarizes the paper and shows our roadmap for future ...