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A dual-band switchable harmonic receiver for downconverting the industrial-scientific-medical and local-multipoint-distribution-service bands at 24 and 31 GHz is proposed in this paper. The front end utilizes a new technique for band selection. Mathematical formulation, including the effect of mismatches, for the new switchable harmonic receiver is...
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The design of frequency synthesizers is especially challenging for wireless applications due to the requirements for high spectral purity, high frequency range, and fast tuning together with reasonable power consumption. The idea of combining digital and analog synthesis techniques for achieving these goals is discussed and analyzed. The proposed a...
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... The development of mobile devices and the need for high-speed communication have resulted in considerable research on receivers operating in the mm-wave frequency bands [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. In [2][3][4], the beamforming receivers were implemented by combining four channels [2,3] and eight channels [4], respectively. ...
This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.
... On the other side, a novel approach in [14] offers a dualband self-oscillating mixer topology, where the fundamental and the second harmonic of the LO was used to mix with the set of complementary switches. In another similar effort [20], the third harmonic component of LO in addition to the fundamental was used for the mixing with the input signal to get the desired band selection at the IF port. Reconfigurability to the spectrum has been an attractive tool to bring in flexibility in the performance of the RF system like mixers, antenna and Low Noise Amplifiers (LNAs). ...
... But the circuit architectures with inductor implementation impose compatibility and chip area issues, as the inductor design consumes a lot of silicon area. Sometimes a negative impedance circuit is used in the mixer design where the capacitor in negative feedback offers an active inductive loading and hence tunes the tail node parasitic for resonance [20]. Figure 5 depicts the proposed down conversion Gilbert cell-based mixer's architecture. ...
... First of all, to support the high data rate needed in fifth generation (5G) communication, unused millimeter-wave (mm-wave) frequency range including Ka-band has become a very attractive candidate. The 5G transceiver operating at Ka-band was studied in many previous works as a result [4][5][6][7]. Another application of the Ka-band frequency range is ultra wideband (UWB) automotive radar system. ...
A broadband receiver front-end with low noise figure and flat conversion gain response is presented in this paper. The receiver front-end is a part of the broadband spectrum sensing receiver and processes 30–40 GHz of broad input spectrum followed by down-conversion to DC-10 GHz of IF signal. The proposed work is comprised of a low noise amplifier (LNA), on-chip passive Balun, down conversion mixer, and output buffer. To achieve front-end target specification over 10 GHz input bandwidth, the stagger-tuned LNA is employed and the down conversion mixer is loaded with a 3rd-order LC ladder low pass filter. The prototype chip was implemented in 45 nm CMOS technology. The chip achieves 10.3–16.5 dB conversion gain, 5.9 dB integrated NF, and −11 dBm IIP3 from 30 to 40 GHz. The chip is realized within 0.42 mm 2 and consumes 96 mW from a 1.2 V supply.
... By selecting either the fundamental or 2 nd order harmonic output of the oscillator as the LO through a set of complementary switches, a dual-band self-oscillating mixer was proposed in [7]. Similarly, band selection was achieved by either mixing the input signal with the fundamental or 3 rd order harmonic component of the LO in [8]. A reconfigurable passive subharmonic mixer (SHM) with a multi-stage injection locked ring oscillator as LO was proposed in [9] for dual-band applications. ...
In this paper, we propose, investigate, and demonstrate a reconfigurable low-voltage and low-power millimeter-wave mixer in 65-nm CMOS, which can be switched as either a subharmonic mixer (SHM) or a fundamental mixer (FM) for dual-band applications. Based on a modified Gilbert mixer topology, the proposed CMOS mixer can operate at low supply voltage and low local oscillator (LO) pumping power while providing a good performance in both SHM and FM modes. To the best of our knowledge, this is the first reported Gilbert SHM based on stacked switching quads in low-voltage CMOS technology. Under 1 V supply voltage and -3 dBm LO pumping power, the measured conversion gain (CG) of the proposed CMOS mixer is -4.8 ± 1.5 dB from 34 to 56 GHz and -0.1 ± 1.5 dB from 17 to 43 GHz in the SHM and FM modes, respectively. The measured double-sideband (DSB) noise figure (NF) is 18.5-20 dB from 37 to 49 GHz and 12.4-14 dB from 17 to 35 GHz in the SHM and FM modes, respectively. The measured input third order intercept point (IIP3) is 2.9 dBm and 3.4 dBm respectively for the SHM and FM modes at LO frequency of 22 GHz. In addition, the total dc power consumption of the proposed mixer including output buffers is 7 mW in both operation modes.
... Hence, many efforts have been made to design dual-band receivers [25]- [31]. Different from the traditional mixer-based receivers [25]- [29], concurrent dual-band six-port receivers [30]- [31] feature low cost, easy integration, small circuit size, low power consumption, and compatibility with digital signal processing (DSP). However, the six-port correlator in [30] has two inputs and four outputs. ...
... The system configuration of the proposed concurrent dualband six-port receiver is shown in Fig. 1(a). Similar to other dual-band receivers [25]- [29], the dual-band RF signal is captured by the dual-band antenna (or broadband antenna), filtered by the dual-band bandpass filter (BPF), and preamplified by the dual-band low noise amplifier (LNA). Then, the RF signal goes into one of the input ports of the six-port demodulator, and two LO signals are fed into the remaining two input ports. ...
A concurrent dual-band six-port receiver based on real-valued time-delay neural network (RVTDNN) is proposed in this paper to retrieve two baseband signals from a dual-band radio frequency (RF) signal, concurrently. Different from the traditional six-port correlator, the new passive circuit correlator, which is composed of one power divider and three quadrature couplers, has three inputs and three outputs, resulting in the decreased hardware complexity as well as circuit size, and a reduced power consumption for the system. The new six-port correlator, its output power as well as the baseband signal recovery theory are described and analyzed in detail. The calibration algorithm based on the RVTDNN is adopted to verify the feasibility of the concurrent dual-band receiver based on the proposed correlator circuit. Finally, a practical wideband six-port receiver test bench, which operates from 2 GHz to 3 GHz, is built and tested using common modulated signals. The calculated error vector magnitudes (EVMs) are all less than 2% verifying the correctness of this novel system implementation approach.
... Hence, many efforts have been made to design dual-band receivers [25]- [31]. Different from the traditional mixer-based receivers [25]- [29], concurrent dual-band six-port receivers [30]- [31] feature low cost, easy integration, small circuit size, low power consumption, and compatibility with digital signal processing (DSP). However, the six-port correlator in [30] has two inputs and four outputs. ...
... The system configuration of the proposed concurrent dualband six-port receiver is shown in Fig. 1(a). Similar to other dual-band receivers [25]- [29], the dual-band RF signal is captured by the dual-band antenna (or broadband antenna), filtered by the dual-band bandpass filter (BPF), and preamplified by the dual-band low noise amplifier (LNA). Then, the RF signal goes into one of the input ports of the six-port demodulator, and two LO signals are fed into the remaining two input ports. ...
A concurrent dual-band receiver based on a single multiport correlator is proposed in this paper to down-convert dual-band radio frequency (RF) signals. The system configuration, output power as well as its spectrum analysis are discussed, and then a generalized baseband signal recovery theory is put forward. Next, the calibration algorithm based on real-valued time-delay neural network (RVTDNN), which can take the system impairments and signal distortions into consideration, is proposed to retrieve two baseband signals, simultaneously. Finally, the six-port receiver is tested under the common modulated signals, and the measured error vector magnitudes (EVMs) between the transmitted and the received signals are all less than 2%.
... The mixer follows an LNA in a silicon-based receiver, and hence, the input matching is not an important requirement as in the case of a stand-alone mixer. The proposed mixer is employed in the architecture of a -wave/mm-wave dual-band switchable harmonic receiver and is described very briefly in [15]. The paper is organized as follows. ...
This paper presents a 20-32-GHz wideband BiCMOS mixer with an IF bandwidth of 12 GHz. The mixer utilizes an inductive peaking technique to extend the bandwidth of the downconverted IF signal. To our knowledge, the proposed mixer achieves the widest IF bandwidth using silicon-based technologies in K-band. Analytical expressions for the conversion gain and output noise of the proposed mixer are presented. The wideband mixer is implemented using 0.18-μm BiCMOS technology and occupies an area of 0.19 mm<sup>2</sup>. It achieves a conversion gain of 3 dB, a noise figure between 10.5 and 13.0 dB, and an IIP3 higher than 0.5 dBm with a power consumption of 18 mW from a 1.8-V supply.
In this brief, a dual-band complementary metal-oxide-semiconductor (CMOS) down-conversion mixer is presented, which supports the fifth-generation new radio frequency bands of 26-30 GHz and 37-40 GHz. In the proposed design, the transformer-based inductance adjustment techniques are utilized to handle dual-band radio frequency and local oscillator (LO) signals for performance optimization. The proposed design is fabricated using a 65-nm CMOS process. With an identical LO power of +5 dBm, the implemented down-conversion mixer attains conversion gains of 7.1 dB and 5.1 dB, noise figures of 9.6 dB and 11.4 dB, input 1-dB compression points of -14.7 dBm and -11 dBm, and input third-order intercept points of -5.1 dBm and -1.95 dBm for 28 and 39 GHz frequency bands, respectively. The implemented design consumes the current of 6.2 mA with a 1-V supply.
