Fig 12 - uploaded by Hong-Yeh Chang
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Measured output spectrum of the BPSK modulator with the LO frequency of 49 GHz and the baseband frequency of 5 MHz.
Source publication
CMOS broad-band compact high-linearity binary phase-shift keying (BPSK) and IQ modulators are proposed and analyzed in this paper. The modulators are constructed utilizing a modified reflection-type topology with the transmission lines implemented on the thick SiO<sub>2</sub> layer to avoid the lossy silicon substrate. The monolithic microwave inte...
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Citations
... In [19] is presented a 30 -40 GHz MMIC IQ vector Modulator with pHEMT transistors functioning as variable resistors, with 5 dB of minimum insertion loss, ±2 • phase error and ±0.3 dB amplitude imbalance. In [20] the authors show a much wideband IQ vector modulator, made in a 0.13 µm CMOS process, with 20 -40 GHz frequency range, less than 13 dB of minimum insertion loss and modulation bandwidth larger than 1 GHz. A BPSK modulator in a MMIC GaAs process is shown in [22] where even higher bandwidth (40 GHz) is achieved, from 25 to 65 GHz, modulation bandwidth greater than 500 MHz, minimum insertion loss less than 10 dB, less than 6 • of phase imbalance and less than 0.9 dB of amplitude imbalance. ...
Vector modulators (VM) and phase shifters are essential components in phased array antennas with electronic beam steering. This work presents an IQ reflection-type vector modulator using PIN diodes, designed and implemented to operate at 28 GHz. An extensive characterization was carried out, especially concerning bandwidth and input/output return losses. This modulator is capable of producing a 360° phase shifting with a minimum attenuation of 14 dB at 28 GHz, and has a measured bandwidth of 3.6 GHz. A digital control system for the vector modulator was also developed, allowing to obtain pre-selected constellations points, with a measured 0.4 dB of maximum absolute error in amplitude and 2.6° in phase. Additionally, the designed VM was employed in a practical application, where analog beamforming is implemented in a
$4\times 4$
transmitter phased array allowing to perform a complete electronic control of the radiation pattern of the array.
... There also exist significant research efforts to develop narrowband miniaturized hybrids constructed with printed circuit boards (PCBs) [19][20][21] and monolithic microwave integrated circuits (MMIC) technology [2,15,[22][23][24]. It should also be noted that MMIC 90 • hybrids with wide bandwidths have been reported at mm-wave frequencies [25][26][27][28]. ...
... In addition, the 60-GHz direct conversion transmitter with 33-dB conversion gain and the 11-dBm saturated power enlarges the dynamic range for the measurement consideration. By using the characteristics of the high image rejection and good LO signal suppression, the direct-conversion transmitter MMIC demonstrates a 1024-QAM modulated signal (modulation capability) with a data rate of 500 Mb/s and the EVM results are within 1.7% at 65 GHz. Figure 13 shows a comparison between our design and other works of MMW high-order QAM modulation [150][151][152][153]. ...
... Among the wideband, miniature, and high isolation, the point is mainly about the passive such as balun, combiner, filter, power divider and matching networks. Note that in [152] and [153], there's no active device in both of the architectures; therefore, no dc power consumptions are required. ...
... Comparison of the MMW high-order quadrature amplitude modulation QAM modulation. Data taken from [146,[150][151][152][153]. 20 ...
In this paper, the advances of the silicon-based millimeter-wave (MMW) monolithic integrated circuits (MMICs) are reported. The silicon-based technologies for MMW MMICs are briefly introduced. In addition, the current status of the MMW MMICs is surveyed and novel circuit topologies are summarized. Some representative MMW MMICs are illustrated as design examples in the categories of their functions in a MMW system. Finally, there is a conclusion and description of the future trend of the development of the MMW ICs.
... RF signal generation and reception in CMOS chips is now routine; CMOS modulator/demodulator for Gigabit millimeter-wave applications had been reported in the literature. In [21]- [23], the design of millimeterwave IQ modulator using CMOS, RF CMOS and CMOS SOI processes achieved modulation bandwidth of 1 GHz, 4GHz and 14 GHz respectively. Reported chip area is 0.65x0.58 ...
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We present details of our proposal as well as the results of simulations and experiments, which demonstrate the merits of this approach. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW is sufficient to transmit the 64 DDR bits. The overall aggregated bus data rate achieves 240 GB data transfer with the error vector magnitude not exceeding 2.26% and phase error of 1.07 degrees or less.
... An error vector magnitude (EVM) of 28 dB (4%) under the data rate of 480 Mb/s was achieved due to the high linearity and accurate in-phase/quadrature (IQ) modulation. A broadband binary phase-shift keying (BPSK)/IQ modulator was reported in [6]. The system was implemented on a thick SiO to achieve a lower loss compared to a silicon substrate. ...
An RF photonic quadrature phase-shift keying (QPSK) modulator is conceived and demonstrated practically. The modulator has the ability to operate with any RF carrier frequency within an ultra-broad frequency range. This is achieved via utilization of a broadband Hilbert transformer. The transformer enables wideband 90$^{circ}$ phase shifts required for QPSK to be realized. The carrier frequency independent operation of this modulator makes it a perfect candidate for many applications such as electronic warfare transmitters operating based on frequency hopping. An operational frequency range of 9.8–30.2 GHz was achieved.
... Reducing the form factor, on-chip balun offers capabilities of high integration and causes less parasitic effects due to shorter interconnections to devices. For high tolerance of process variations , a wideband, passive Marchand-type balun is used [26], [27].Fig. 18 shows the simplified transmission line configuration and the physical layout of the on-chip Marchand balun. ...
This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag<sub>m</sub>-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g<sub>m</sub>-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm<sup>2</sup>. The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.
... To further reduce the size of the hybrid, the coupler in the Marchand balun is broadside-coupled. Chang et al. [13] has shown that the broadside-coupled Marchand balun with the same terminated impedances in the bulk CMOS process demonstrated excellent measured amplitude/phase match, broadband frequency response, and ultra-compact area based on the assumption of a small difference between the normalized propagation constants of the two metal lines in the broadside coupled TFMS lines so that the coupled lines can be treated as the symmetric coupled lines. This criterion will be satisfied if the ratio of the dielectric thickness between top two metals to the total substrate thickness of the TFMS lines is low enough. ...
The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design methodology. The monolithic microwave integrated circuit mixers achieve comparable performance with a compact chip size among the reported 60-GHz CMOS mixers.
... Modern direct frequency modulator's performance is limited by its non-linear phase shifter. Passive phase shifters, for example, utilize bi-phase modulators which receive reflected signals from a variable resistance cold-FET [1] or varactor [2] via a 90 o hybrid. Resistance/capacitance variation may change their phase and precise bias controls are necessary to track the nonlinear R-V or C-V relationship. ...
A digitally controlled artificial dielectric (DiCAD) differential transmission line is designed to perform agile linear phase shift over 100deg with thermometer-coded 16 step control. It also operates with a 16 gain-step VGA to enable re-configurable and direct-frequency modulation at 60 GHz with 256<sup>2</sup> states (1.1deg angular and 0.0007 magnitude resolutions) and -31 dB static EVM for multiple PSK/QAM modulations. The modulator uses 0.33 mm<sup>2</sup> core area in 90 nm CMOS and consumes 10 mA at 1 V.
... Our VCO features a superior phase noise at 1 MHz offset frequency for the fundamental oscillation frequency of 98.6 GHz. The mode selector is based on a modified reflection-type BPSK modulator [13] ...
... Our VCO features a superior phase noise at 1 MHz offset frequency for the fundamental oscillation frequency of 98.6 GHz. The mode selector is based on a modified reflection-type BPSK modulator [13] due to its low phase and amplitude imbalances. The second harmonic of the fundamental mode and fundamental suppression of the push-push mode are both better than . ...
... The concept of mode selection is based on the in-phase or 180 out-of-phase power combining. The configuration of the VCO with the two reflection-type modulators is similar to the modified reflection-type BPSK modulator [13]. The modulators perform 180 out-of-phase and the in-phase power combining when the VCO is operated in fundamental and push-push mode, respectively. ...
A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than -8 dBm. The phase noise of the VCO is better than -100.8 dBc/Hz at 1 MHz offset frequency, and its figure-of-merit is better than -186 dBc/Hz. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than -30 dBc as the VCO is operated in push-push mode.
... The BCS lines allow the integration of miniature 1 : 4 passive dividers without any crossovers, and result in a 1 : 8 divider with excellent phase and amplitude balance at 40-50 GHz. Recently, asymmetric BCS lines have been used in a 0. 18 process for a low-loss balun [3], and symmetric lines are used in [4] for a partly shielded balun, but these incompletely shielded implementations are not optimal for densely packed power dividers. Other power dividers include the uniplanar monolithic microwave integrated circuit (MMIC) structure [5], [6] and transformer-based dividers [7]. ...
... However, the eight differential amplifiers following the 1 : 8 power divider and the eight DTS amplifiers at the output nodes consume 2 46 mA. The DTS amplifiers can be replaced by passive baluns in future designs [4], [6] or can be omitted when used in a differential phasedarray chip. As indicated in Fig. 9, the internal 1 : 8 power-divider stage consumes only 17 mA of current for a gain of 4.7 dB at 45 GHz and includes the 1 : 8 split loss (9 dB) and the 1 : 4 BCS power-divider loss (3.2 dB). ...
This paper presents a 1 : 8 differential power divider implemented in a commercial SiGe BiCMOS process using fully shielded broadside-coupled striplines integrated vertically in the silicon interconnect stackup. The 1 : 8 power divider is only 1.12 x1.5 mm<sup>2</sup> including pads, and shows 0.4-dB rms gain imbalance and <3deg rms phase imbalance from 40 to 50 GHz over all eight channels, a measured power gain of 14.9 plusmn0.6 dB versus a passive divider at 45 GHz, and a 3-dB bandwidth from 37 to 52 GHz. A detailed characterization of the shielded broadside-coupled striplines is presented and agrees well with simulations. These compact lines can be used for a variety of applications in SiGe/CMOS millimeter-wave circuits, including differential signal distribution, miniature power dividers, matching networks, filters, couplers, and baluns.
