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Matrix-DSP architecture.

Matrix-DSP architecture.

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Figure 1. Discrete format of partial differential equations in a...
Figure 2. 3D mantle convection finite-element-structured grid...
Figure 3. ELL format based on 5-point discrete format on a 4 × 4 grid.
Figure 4. Matrix-DSP architecture.
+4 Figure 5. Blocking method and multicolor reordering method.
Improving Structured Grid-Based Sparse Matrix-Vector Multiplication and Gauss–Seidel Iteration on GPDSP
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  • Aug 2023
Structured grid-based sparse matrix-vector multiplication and Gauss–Seidel iterations are very important kernel functions in scientific and engineering computations, both of which are memory intensive and bandwidth-limited. GPDSP is a general purpose digital signal processor, which is a very significant embedded processor that has been introduced i...
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... Matrix-DSP uses the very long instruction word (VLIW), which can launch five scalar instructions and six vector instructions simultaneously, for a total of eleven instructions. The overall architecture of the Matrix-DSP, shown in Figure 4, consists of a scalar processing unit (SPU) for scalar computation and flow control, as well as a vector processing unit (VPU) for vector computation. The VPU consists of 16 64-bit vector processing elements (VPEs) that support vector computation with a total length of 1024 bits. ...