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Consider a hypercube of 2<sup>n</sup> points described by n
Boolean variables and a subcube of 2<sup>m</sup> points, m⩽n. As is
well-known, the Boolean function with value 1 in the points of the
subcube can be expressed as the product (AND) of n-m variables. The
standard synthesis of arbitrary functions exploits this property. We
extend the con...
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Context 2
... express s i in SPP, we represent our functions in the recursive maps of Fig. 6 (not necessarily Karnaugh maps) that are easily constructed from the definition of sum and carry. Each submap containing a function (e.g., the submap of s i for i i HH, containing i ) recursively stands for the map of that function (i.e., the map of i labeled with ...
Context 3
... examples of auto-symmetry are exhibited by the functions s i (sum) and i (carry) of an n-bit adder, discussed in Section 5. Refer to the definition of s i and i as presented in the maps of Fig. 6. Consider a map labeled j , j . After the recursive substitutions of the submaps, the columns (respectively, the rows) of the map become labeled with ...
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Citations
... Autosymmetric Boolean functions are functions that exhibit a structural regularity based on the notion of affine spaces and are easily expressed using XORs. They were introduced in [20] and further studied in [4], [8], [9], [18], where it was shown how this regularity can be exploited to derive, in shorter synthesis time, compact logic representations for CMOS technology. More recently, the autosymmetry property has been applied in logic synthesis for emerging technologies, i.e., Switching Nano-Crossbars [7], and to better estimate the multiplicative complexity of functions for security protocols [5], [41]. ...
... Autosymmetric Boolean functions [9], [10], [20] exhibit a special type of regularity based on the notion of affine spaces and are easily expressed using XORs. A function f over n variables is autosymmetric if it can be projected onto a function depending on a smaller number of variables and containing a reduced number of minterms. ...
We propose a new three-level XOR-AND-XOR form for autosymmetric functions, called XORAX expression. In general, a Boolean function f over n variables is k-autosymmetric if it can be projected onto a smaller function fk, which depends on n-k variables only. We show that XORAX expressions can ease the reversible synthesis of autosymmetric functions, producing compact reversible networks, without inserting additional new input lines. Autosymmetry occurs especially for functions that exhibit a regular structure, as for instance arithmetic functions. For this reason, compact reversible networks for autosymmetric functions might be interesting for quantum computing. Experimental results validate the proposed approach.
... The polarity variables p i, j play the same role as defined for ESOP forms, i.e., the parity function L i in term j is negated if p i, j = 0, used as is if p i, j = 1, and omitted if p i, j = 2. The terms in (6) are called pseudoproducts [27]. Note that each ESOP is also an ESPP, but an ESPP is only an ESOP if (p i, j 2) → (ν (i) = 1) (where ν (i) is the sideways sum of i, i.e., the number of 1s in its binary expansion). ...
The multiplicative depth of a logic network over the gate basis $\{\land, \oplus, \neg\}$ is the largest number of $\land$ gates on any path from a primary input to a primary output in the network. We describe a dynamic programming based logic synthesis algorithm to reduce the multiplicative depth in logic networks. It makes use of cut enumeration, tree balancing, and exclusive sum-of-products (ESOP) representations. Our algorithm has applications to cryptography and quantum computing, as a reduction in the multiplicative depth directly translates to a lower $T$-depth of the corresponding quantum circuit. Our experimental results show improvements in $T$-depth over state-of-the-art methods and over several hand-optimized quantum circuits for instances of AES, SHA, and floating-point arithmetic.
... Affine equivalence plays an important role in cryptography, since many cryptographic properties of Boolean functions remain the same after affine transformations [13], [19]. Algebraic degree, as a key cryptographic property of Boolean functions, has many applications in the area [17], [18]. ...
Affine equivalence classes of Boolean functions has many applications in modern cryptography and circuit design. Previous publications have shown that affine equivalence on the entire space of Boolean functions can be computed up to 10 variables, but not on the quotient Boolean function space modulo functions of different degrees. Computing the number of equivalent classes of cosets of Reed-Muller code $\mathcal{R}(1,n)$ is equivalent to classifying Boolean functions modulo linear functions, which can be computed only when $n\leq 6$. In this paper, we propose a novel method to compute the number of affine equivalence classes on the quotient space of different degrees of Boolean functions $\mathcal{B}(s,n)/\mathcal{B}(k,n)$, where $\mathcal{B}(s,n)$ is the set of Boolean functions with degree $\leq s$. By constructing linear representation of the affine group $\mathcal{AGL}(n,2)$ on the quotient Boolean function space, we obtain a useful counting formula to classify Boolean functions on the quotient spaces. With the proposed algorithm, the number of equivalent classes of cosets of $R(1,n)$ can be computed up to 10 variables and the results are presented in this paper. Furthermore, the number of affine equivalent classes on the quotient space $\mathcal{B}(s,n)/\mathcal{B}(k,n)$ can also be computed when $-1\leq k< s\leq n\leq 10$, which is a major improvement and advancement comparing to previous methods.
... Multi-level minimization Unbounded multilevel minimization algorithms SIS (3) and BDD Based circuit (4,9) are very fast and the resulting network is often compact. Bounded multi level EXSOP (7), OR-AND-OR (8), SPP (9) &EPSOP(8&1)and the bound promising for high quality but huge minimization time required for their synthesis. KEP-SOP form minimization, an approximation algorithm which guarantee near optimum solution with polynomial time and utilize the projection of SOP form into subspaces of Boolean space that reduces the hamming distance among the cube appearing in each subspaces (1). ...
Full testability is a desirable property network and maintaining the testability of multi-level logic synthesis is very complicated. In our paper propose new technique which maintains fully testable circuit with function mode under the robust path delay fault model. The preservation of testability of these networks under the stuck-at-fault model and Path delay model, preservation of testability the K-EPSOP is typical but it we proposed robust path delay fault model using binate property of variable with mux realization for remainder or without remainder. The whole our new architecture gives guarantees the path delay fault fully testable circuit a modification in design and operates on mode e.g. functional mode.
... A function may also be degenerate in k > 1 variables, and its algebraic form depends upon the remaining n − k variables. In fact, degeneration is a special case of a general form of function regularity known as autosymmetry [1,2,17]. ...
... In step (ii) the new function f k can be synthesized in any framework of logic minimization, e.g., two level logic as SOP [7], Reed Muller [18]; three-level logic as SPP [4,17] (OR of ANDs of EXORs), EXSOP [9,10] (EXOR of ORs of ANDs); or general multi-level minimization [12,14]. In general we can observe that, in any logic framework, the time required by the minimization of f k is obviously less than the time required for the minimization of f , since f k is defined on a smaller space (more precisely, f k depends only on n − k variables and has |f |/2 k points). ...
Autosymmetric functions exhibit a special type of regularity that can speed-up the minimization process. Based on this autosymmetry,
we propose a three level form of logic synthesis, called ORAX (EXOR-AND-OR), to be compared with the standard minimal SOP
(Sum of Products) form.
First we provide a fast ORAX minimization algorithm for autosymmetric functions. The ORAX network for a function f has a first level of at most 2(n−k) EXOR gates, followed by the AND-OR levels, where n is the number of input variables and k is the “autosymmetry degree” of f. In general a minimal ORAX form has smaller size than a standard minimal SOP form for the same function. We show how the
gain in area of ORAX over SOP can be measured without explicitly generating the latter. If preferred, a SOP expression can
be directly derived from the corresponding ORAX. A set of experimental results confirms that the ORAX form is generally more
compact than the SOP form, and its synthesis is much faster than classical three-level logic minimization. Indeed ORAX and
SOP minimization times are often comparable, and in some cases ORAX synthesis is even faster.
... Logic circuits that include XOR gates have some advantages over traditional circuits with only AND and OR gates. An XOR-based realization can improve testability [4] and often reduces the circuit area [5]. AND/XOR logical expressions have been studied as the fundamentals of the XOR-based realization. ...
This paper proposes a novel method to improve the utilization efficiency and performance of field-programmable gate arrays (FPGAs). The proposed method, ExorBDD, uses a stage of exclusive-sum-of-product (ESOP) minimization, followed by a stage of decomposition using binary decision diagrams (BDDs). For exclusive OR (XOR)-intensive circuits, experiments were conducted on 19 MCNC benchmark parity circuits (ranging from 5 to 25 inputs), as they are the most representative case of XOR-intensive circuits. The results using the proposed approach show significant improvements over Exorcism4, BDS, and commercial tools. On average, the new approach uses only 30.3% as many look-up tables as are used by Xilinx tools (and only 16.4% in comparison to Altera). On average, the new approach has a maximum combinational path delay of 89.2% compared to the delay with Xilinx tools (80.3% compared to Altera). Experiments were also conducted on non-XOR-intensive circuits. These results show that ExorBDD also performs well for arbitrary circuits.
... Several restrictions to the structure of a circuit have been considered to meet certain goals during synthesis (see e.g. [16,11,9,12,10,6,14,13]). Promising approaches that already consider testability are circuits based on Binary Decision Diagrams (BDDs), so called BDD circuits [1], and Sum of Pseudoproduct (SPP) networks [6]. ...
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100% testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.
... The drawbacks of this approach are the unbounded number of levels (and therefore the longer delay), as well as the much larger computational time required to synthesize the network. In an attempt to establish an effective trade-off between these two opposite approaches, recent studies have proposed the optimization of networks with a fixed number of levels (typically, three or four levels) [1,5,6,7,13,15,17]. Sasao statistically showed that three levels of logic are enough to produce a minimal network for most of the Boolean functions; and in many cases three-level logic is a good compromise between circuit speed, circuit size, and the time needed for the minimization procedure [16]. ...
In this paper, the authors introduce a new algebraic form for Boolean function representation, called EXOR-projected sum of products (EP-SOP), resulting in a four level network that can be easily implemented in practice. The authors prove that deriving an optimal EP-SOP from an optimal sum of products (SOP) form is a hard problem (NP <sup>NP</sup>-hard); nevertheless the authors propose a very efficient approximation algorithm, which returns in polynomial time an EP-SOP form whose cost is guaranteed to be near the optimum. Experimental evidence shows that for about 35% of the classical synthesis benchmarks the EP-SOP networks have a smaller area and delay with respect to the optimal SOPs (sometimes gaining even 40-50% of the area). Since the computational times required are extremely short, the authors recommend the use of the proposed approach as a postprocessing step after SOP minimization
... , EXSOP [Chattopadhyay et al., 1997, Debnath and Sasao, 1999, Dubrova et al, 1999, OR-AND-OR [Debnath and Vransic, 2003], SPP [Ciriani, 2003b, Luccio andPagli, 1999], ESPP [Ishikawa et al, 2002]), is critical and depends on multiple factors. Moreover it is very difficult to define a theoretical model that captures the problem in its generality. ...
... In this paper we focus on a special three-level network called Sum ofPseudoproducts (SPP) and on the more general Sum of k-Pseudoproducts (k-SPP), This choice is motivated by the fact that SPP networks often satisfy the above mentioned properties: SPP expressions, introduced in [Luccio and Pagli, 1999], can be seen as a direct generalization of SOP expressions using EXOR gates. An SPP form consists of the OR of pseudoproducts, where a pseudoproduct is the AND of EXOR factors (i.e., EXOR of literals). ...
... The SPP forms, proposed and studied in [Ciriani, 2003a, Ciriani, 2003b, Luccio and Pagli, 1999, are a direct generalization of 2-SPP expressions, where the EXOR factors can have an unbounded number of literals. ...
Recently introduced, three-level logic Sum of Pseudoproducts (SPP) forms allow the representation of Boolean functions with much shorter expressions than standard two-level Sum of Products (SOP) forms, or other three-level logic forms. In this paper the testability of circuits derived from SPPs is analyzed. We study testability under the Stuck-At Fault Model (SAFM). For SPP networks several minimal forms can be considered. While full testability can be proved for some classes, others are shown to contain redundancies. Experimental results are given to demonstrate the efficiency of the approach. Full Text at Springer, may require registration or fee
... In [3] the regularity of a Boolean function f over a set X = {x 1 , . . . , x n } of n Boolean variables has been expressed by its autosymmetry degree k, with 0 ≤ k ≤ n, and it has been shown how autosymmetry allows decreasing the time needed for three-level logic synthesis (in particular for the so-called Sum of Pseudoproducts, or SPP, synthesis [8], [22]). The function f is autosymmetric over k variables if there exists a function f k over n − k variables, y 1 , y 2 , . . ...
... The new function f k (y 1 , . . . , y n−k ) can now be synthesized in any framework of logic minimization, e.g., two-level logic as SOP [11], Reed Muller [15], [27]; three-level logic as SPP [8], [22] (OR of ANDs of EXORs), EXSOP [12], [13], [14] (EXOR of ORs of ANDs); or general multi-level minimization. In the SPP framework this method is particularly convenient because the new EXOR level can be merged with the first level of EXORs in the SPP form, thus the number of levels does not increase [3]. ...
... The autosymmetric functions that we review in this section were introduced in [22] and studied in [3]. Given two binary vectors α, β, let α ⊕ β be the elementwise EXOR between α and β. ...
The "regularity" of a Boolean function can be exploited for decreasing its minimization time. It has already been shown that
the
notion of autosymmetry is a valid measure of regularity, however such a notion has been studied thus far either in the theoretical
framework of self-dual Boolean functions, or for the synthesis of a particular family of three-level logic networks. In this
paper we show that the degree of autosymmetry of an arbitrary function can be computed implicitly in a very efficient way,
and autosymmetry can then be exploited in any logic minimization context. Our algorithms make crucial use of Binary Decision
Diagrams. A set of experimental results on the synthesis of standard benchmark functions substantiates the practical relevance
of our theoretical results.
