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This tutorial presents a cohesive view of power-conscious system-level design. We consider systems as consisting of a hardware platform executing software programs. We address the problems of power estimation and minimization for such systems. We consider the major constituents of systems: processors, memories and communication resources. We analyz...
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... In this case the power up/down sequences consume four clock cycles, plus the number of cycles that are required to bring the power rails to the required supply voltage. Many surveys [Benini and Micheli 2000; Verma et al. 2015] suggest combining PSO with CG for maximizing power savings. When the switchable domain is powered down, we gate its clock nets at the time of power down. ...
... Similarly, they emphasize adopting low power schemes such as MSV, PSO, CG, and DVFS at the RTL, while using gates with varying transistor widths to achieve additional energy saving at the gate- level. Schirrmeister [12] , and Benini and Micheli [13] provide a review of the different abstraction levels for energy measurement and estimation as well as common techniques to optimize a design for low power above RTL. They use a typical JPEG decoder as a test case. ...
... In this case the power up/down sequences consume four clock cycles, plus the number of cycles that are required to bring the power rails to the required supply voltage. Many surveys [13,35] suggest combining PSO with CG for maximizing power savings . When the switchable domain is powered down, we gate its clock nets at the time of power down. ...
ion level for digital designs is rising from Register Transfer Level (RTL) to algorithmic untimed or transaction-based, followed by an automated high-level synthesis (HLS) flow. However, it is still a significant challenge for chip architects and designers to describe low-power design decisions at the system-level. Nowadays, low power design techniques for digital blocks are applied at RTL and there exists no commercial tool or methodology that can automatically derive the power intent from the system-level description. The process requires considerable amount of human intervention and various low-level details that are needed to implement low power schemes at RTL. This research aims to integrate low power techniques, specifically Power Shut-Off (PSO), within a model-based hardware flow and to derive an automated Low Power-High Level Synthesis (LP-HLS) methodology. The methodology aims at minimizing the design effort for low power design by deriving low-level power intent automatically for model-based designs, while using high-level synthesis to achieve a broad set of target system implementations. LP-HLS uses set of pragmas and a directive file to derive power intent information. To illustrate the methodology, three model designs, ranging from simple designs to medium complexity hardware accelerators, are considered. Finally, the power saving results for the design scenarios validate the effectiveness of our LP-HLS methodology.
... Another instruction compression technique has been presented in Ref. [24] is Thumb Instruction set of ARM processor which can be programmed to use the set of 16 bit instruction as compared to 32 bit instruction set. Various system level power optimization techniques have been presented in Ref. [25] are memory optimization techniques , hardware-software partitioning, instruction-level power optimization, control-data-flow transformations, variable-voltage techniques, dynamic power management, interface power minimization and approximate signal processing . In Refs. ...
... Another instruction compression technique has been presented in Ref.[24]is Thumb Instruction set of ARM processor which can be programmed to use the set of 16 bit instruction as compared to 32 bit instruction set. Various system level power optimization techniques have been presented in Ref.[25]are memory optimization techniques, hardware-software partitioning, instruction-level power optimization, control-data-flow transformations, variable-voltage techniques, dynamic power management, interface power minimization and approximate signal processing. In Refs.[26,27]system level optimization is used to obtain the perfect performance of electric drive systems. ...
Ultra low power CMOS digital integrated circuits are the enabling technology for the modern portable and
bio-inspired systems. The efficiency of these systems has been realized with requirement of low power for
their operation. As for the fulfillment of the requirement of present technological world, we are on the way to
commercialize these devices to the nano scale. Higher functionally and higher performance of digital circuits
are required at lower power consumption. So with the increasing need of ultra-low-power digital circuits, study
of less power VLSI design has grown one of the most essential influences in continuous development of
nano electronics. This survey focuses on the various considerations in ultra low power CMOS VLSI designs
for broad class of portable and bio-inspired system architectures. Consideration of remedies of large power
benefits in low power consumption by digital devices even below 45 nm technologies. However, in spite of
their importance in advancement of ultra low power digital VLSI design for recent technology, these power
reduction methods and their comparisons have never been surveyed so far. The essential aim of this paper is
to fill the existing gap by addressing an extensive review of sources of power dissipation, power approximation
and optimization techniques at different level of design abstraction layers, various technologies for ultra-lowpower
design and their implementation in bio-inspired systems. A tabular representation of various power
reduction methods and comparison of different power reduction techniques has been presented. This paper
goes through the detailed review of energy recovery logic called adiabatic logic for ultra-low-power design by
discussing various fully and partially adiabatic logic styles. After presenting the above low power technologies
this paper discusses the potential of these technologies in emerging trends of bio-inspired systems.
... The topic of energy reduction has been intensively studied in the literature and is being investigated at all levels of system abstraction, from the physical layout to software design. There have been several contributions on energy saving focused on scheduling/processors [6][7][8], data organizations [9, 1] , com- pilation [17][18][19] 24], and the algorithmic level [21, 22, 24]. The research at the Corresponding author architecture level has led to new and advanced low energy architectures, like the Mobile SDRAM and the RDRAM, that support several low power features such as multiple power states of memory banks with dynamic transitions [11, 12] , row/column specific activation, partial array refresh, and dynamic voltage/frequency scaling [20]. ...
... The process of modern DSE is heavily reliant on user objectives of power and delay. Because of remarkable escalation in the demand of personal computing devices with limited battery life, power as a design objective has become the front runner of current research [17, 18, 19]. Generally, considering power during DSE in HLS is also motivated because of the following reasons: ...
Digital integrated circuits (ICs) are the main workhorse of all modern consumer electronic systems. Digital ICs are much more complex and more closely follow the technology scaling as compared to the analog or mixed-signal ICs. For example, the transistor count can be in billions the device sizes at this point can be 14 nm FinFET in the digital ICs. However, the good news for digital ICs is that the digital designs have well-defined abstractions including system, architecture, logic. This Chapter is focused at the architecture level of the digital ICs. In particular, detailed discussions of high-level synthesis technique has been presented that can generate digital ICs. Trust of electronic systems that are used in day-to-day life is critical. This Chapter also discusses the HLS technique that can generate trusted digital ICs.
... In recent years, a number of approaches have been proposed for the design of energy-efficient systems. Benini et.al. [9] provide a comprehensive survey, examining techniques for optimizing energy at different levels: modelling, system design and runtime management. The review by Unsal et.al. [31] focuses on techniques enabling low-power design for realtime systems, covering the whole span of architectural levels, from hardware to operating systems and com ...
We develop a novel model-based hardware-in-the-loop (HIL) framework for optimising energy consumption of embedded software controllers. Controller and plant models are specified as networks of parameterised timed input/output au-tomata and translated into executable code. The controller is encoded into the target embedded hardware, which is connected to a power monitor and interacts with the simulation of the plant model. The framework then generates a power consumption model that maps controller transitions to distributions over power measurements, and is used to optimise the timing parameters of the controller, without compromising a given safety requirement. The novelty of our approach is that we measure the real power consumption of the controller and use thus obtained data for energy optimisation. We employ timed Petri nets as an intermediate representation of the executable specification, which facilitates efficient code generation and fast simulations. Our framework uniquely combines the advantages of rigorous specifications with accurate power measurements and methods for online model estimation, thus enabling automated design of correct and energy-efficient controllers.
... In [7], a hardware testbed is developed to simulate the interactions between a formal model of the pacemaker running on a microcontroller and a heart model implemented on a FPGA. Methods for evaluating and optimizing energy consumption in electronic and embedded systems include [2], [5]. Surrogate-based optimization has been used for a number of engineering applications, including hardware-in-the-loop frameworks (see [6], [13]). ...
Implantable cardiac pacemakers are medical devices that can monitor and correct abnormal heart rhythms.
To provide the necessary safety assurance for pacemaker software, both testing and verification of the code, as well as testing the entire pacemaker hardware in the loop, is necessary.
In this paper, we present a hardware testbed that enables detailed hardware-in-the-loop simulation and energy optimisation of pacemaker algorithms with respect to a heart model.
Both the heart and the pacemaker models are encoded in Simulink/Stateflow and translated into executable code, with the pacemaker executed directly on the microcontroller.
We evaluate the usefulness of the testbed by developing a parameter synthesis algorithm which optimises the timing parameters based on power measurements acquired in real-time.
The experiments performed on real measurements successfully demonstrate that the testbed is capable of energy minimisation in real-time and obtains safe pacemaker timing parameters.
... The scale down of transistor technology allows microelectronics manufacturers to embed more sophisticated systems on a single micro-chip (SoC) [2], [3], [4], [5], [6], [7]. On chip integration is becoming popular not only in the Chip Multi Processor (CMP) research area but also in the wider range of nowadays devices such as cell-phones, smart-phones, smart-houses and vehicle embedded systems , etc. ...
... Dense Gaussian networks are thus good candidate for NoC interconnection networks. It has been shown in [15], [16] the isomorphism between the dense Gaussian network Gk+(k+1)i and the Circulant C(k, k+1).Fig. 1 (a) and (b) show the isomorphism between G3+4i and C(3,4). Next, we define Dense Gaussian Networks [15]. ...
... This simple operation can be easily implemented by the router hardware. Our all-to-all algorithm uses packetswitching which is the preferred transmission mode for NoC architectures [4]. The presented all-to-all procedure is implemented and runs on every node of the dense Gaussian NoC architectures . ...
Gaussian networks are gaining popularity as good candidates Network On-Chip (NoC) for interconnecting Multiprocessor System-on-Chips (MPSoCs). They showed better topological properties compared to the 2D torus networks with the same number of nodes and the same degree 4. All-to-all broadcast is a collective communication algorithm used frequently in many parallel applications. Recently, Z. Zhang et al. [1] have proposed an all-to-all broadcast algorithm for Gaussian on-chip networks that achieves the minimum delay time but requires 4 extra buffers per router, where is the network diameter. In this paper, we propose a new all-to-all broadcast algorithm for dense Gaussian on-chip networks that achieves the minimum delay time without requiring any extra buffers per router. In this paper, we propose a new all-to-all broadcast algorithm for dense Gaussian on-chip networks that achieves the minimum delay time without requiring any extra buffers per router. Along with low latency, reducing the amount of buffer space and power consumption are very important issues in NoCs architectures.
... Approaches which can reduce power consumption, thereby prolonging battery life, are called lowpower technologies herein ( " power optimization " and " powerefficient design " are terms also commonly used). Low-power technologies have already been widely-used in many areas, such as embedded system design [25] and operating system design [26], and they can encompass many widely differing approaches, including the design of energy-efficient system architectures [27, 28], electronic hardware design [29], dynamic scheduling techniques [30], or efficient signal processing algorithms [31]. Besides saving energy, low-power technologies can also help avoid overheating [32]. ...
Wearable telecare and telehealth systems are those which can be worn on the human body and continuously monitor a user’s vital status. Even though these systems have already shown promise in applications for improving medical service quality and reducing medical costs, a short battery life significantly restricts the widespread use of these systems. Low-power technologies (a general name for technologies which use various approaches to reduce the power consumption of the associated electronics) can help alleviate this disadvantage of wearable telecare and telehealth systems. In this paper, we review recent developments and applications of low-power technologies in wearable telecare and telehealth systems, sorting the various approaches into two categories: hardware-based approaches and firmware-based approaches. This paper focuses on illustrating how to realize these approaches but does not provide a quantitative analysis of different approaches, since the intended applications of these approaches are quite different, hence numeric comparison is not meaningful. Given the proliferation of wearable telecare and telehealth systems, there will be a greater emphasis on the development of low-power technologies in this field.
... Energy reduction is an important research topic, which is being investigated at all levels of system abstraction, from the physical layout to software design. There have been several contributions on energy saving focused on scheduling/processors [10,16,8,33,34], data organizations [35,12], compilation [32,5,23], and the algorithmic level [27,25,16]. Power management in sensors network, where energy is really critical, is addressed in [31]. ...
Power consumption has became a critical concern in modern computing systems for various reasons including financial savings and environmental protection. With battery powered devices, we need to care about the available amount of energy since it is limited. For the case of supercomputers, as they imply a large aggregation of heavy CPU activities, we are exposed to a risk of overheating. As the design of current and future hardware is becoming more and more complex, energy prediction or estimation is as elusive as that of time performance. However, having a good prediction of power consumption is still an important request to the computer science community. Indeed, power consumption might become a common performance and cost metric in the near future. A good methodology for energy prediction could have a great impact on power-aware programming, compilation, or runtime monitoring. In this paper, we try to understand from measurements where and how power is consumed at the level of a computing node. We focus on a set of basic programming instructions, more precisely those related to CPU and memory. We propose an analytical prediction model based on the hypothesis that each basic instruction has an average energy cost that can be estimated on a given architecture through a series of micro-benchmarks. The considered energy cost per operation includes both the overhead of the embedding loop and associated (hardware/software) optimizations. Using these precalculated values, we derive a linear extrapolation model to predict the energy of a given algorithm expressed by means of atomic instructions. We then use three selected applications to check the accuracy of our prediction method by comparing our estimations with the corresponding measurements obtained using a multimeter. We show a 9.48% energy prediction on sorting.
... The Dynamic Voltage/Frequency Scaling (DVFS) policy [2] adjusts at runtime the operating frequency as well as the voltage of electronic components with respect to changing workloads, real-time constraints, etc. One critical problem is that reliable results on power saving policies can only be obtained at low design stages, which might be too late for design consideration [3]. In order to make early power-efficient design decisions, high-level power estimation and optimization would be extremely beneficial. ...
Power consumption has become one of the major concerns in embedded systems design, especially for mobile devices, which integrate many applications leading to a high power consumption. In this context, designers have the challenge to identify power issues early in the design flow and to explore the largest possible space of power-efficient solutions. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach is based on a high-level modeling of power estimation and dynamic management aspects targeting an automatic generation of the corresponding simulation code. It was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile. The existing C++ simulation code generator was extended in order to integrate power estimation. The main objective of this article is to illustrate the potential of our approach through an MPEG-2 case study. The proposed high-level power modeling concepts were used to target two different platforms for the implementation of an MPEG-2 decoding application. The processor power estimates obtained from simulations were compared to real board measurements. This comparison showed that our MDE approach is capable of obtaining results that can be used to make early power-efficient design decisions.
