Main amplifier block diagram. 

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Context 1

... completely analog and generic interface circuit that can solve all the above mentioned problems and makes it easier to integrate the MEMS sensor with commercially available CMOS process as a low cost smart MEMS sensor. Section II discusses the architecture of the sensor and interfacing circuit. Building blocks of the smart MEMS sensor are discussed in section III. In section IV, simulation results are given, followed by conclusion in section V. II. A RCHITECTURE The smart MEMS implemented in this paper consists of a MEMS sensor and an interfacing circuit. The sensor is a uni- axial, quad beam, piezoresistive accelerometer, designed for ±13g acceleration range and low off-axis sensitivity. The total interfacing circuit can be divided into two parts. One part consists of a low offset, low noise, variable gain, instrumentation amplifier along with a peak detector and a gain controlling circuit. The other part consists of a novel circuit for sensor sensitivity and offset temperature compensation. Without any separate temperature sensing unit, this circuit can dynamically compensate the nonlinear temperature dependency of sensor sensitivity and offset. Timing control block generates all clock signals and a fail-safe Triple Modular Redundant (TMR) bias generator block generates all bias voltages and currents. Overall block diagram of the main amplifier and the sensitivity-offset compensation circuit have been shown in Fig.1 and Fig.2 respectively. There are broadly three types of circuit topologies for dynamic reduction of offset and 1/f noise [3], [4]. It is possible to combine two or more of these topologies to obtain a optimized result. Table 1 shows a comparison between these topologies. There are various hybrid topologies reported for low offset and 1/f noise, (as low as 100nV input offset [5]) but all of them have either very low system bandwidth or low dynamic range [6], [7], [8] . In this work the main amplifier is a combination of two well known low offset, low noise topologies, namely chopper and ping-pong auto-zero. Each of the two parallel branches of the main amplifier is auto zeroed and the whole amplifier is put inside a pair of choppers. Chopping frequency is 100kHz (1/f noise corner frequency of the amplifier is around 1kHz). The auto-zero technique prevents the amplifier from becoming saturated due to its own offset, as the input offset of each amplifier will be multiplied by the close loop gain of that amplifier. This hybrid implementation lifts the severe bandwidth limitation of nested chopper amplifier and ping- pong auto-zero provides continuous time output (no loss of information).Each branch consists of four cascaded amplifiers. First amplifier is a fixed gain OpAmp and the rest are of variable gain. The input signal is modulated by the input chopper (C ch is the chopper clock in Fig. 1) and then amplified by cascaded OpAmps. The output chopper demodulates the signal back to its original frequency but modulates the offset and the 1/f noise around 100kHz. The auto-zero switches are operating at 12.5kHz (C az in Fig. 1). Afterwards two types of Low Pass Filters (LPFs) are used to filter out the modulated offset and 1/f noise. First LPF is a second order, differential-in-differential-out, continuous time (using on chip lumped resistances and capacitances) filter with cutoff frequency 10kHz. which is followed by three stages of second order, differential-in-differential-out, variable cut-off frequency Switched Capacitor LPF (SCLPF). The filtered output is fed to a peak detector circuit (PD). Subsequently, two bit digital signal is generated by PD and a Finite State Machine (FSM) is designed to change the gain of the amplifier. The amplifier is designed for a bandwidth up to 5kHz, and a maximum gain of 104dB, with a dynamic range of 84dB. In the 1980’s, temperature dependency of sensor sensitivity and offset were corrected either by special devices whose temperature characteristics are complimentary to that of the original sensor [9] or by modulating the bridge supply [10]. But the compensation was not dynamic and accuracy was very poor. In the 1990’s, some papers reported the use of a second passive bridge for compensation [11]. As the piezoresistivity is a coupled function of stress and temperature, such techniques had the similar draw backs as those of the 1980’s. Later digital techniques were used to store sensitivity and offset data and then compensate the sensor. MAXIM and Microbridge Technologies Inc. came up with highly accurate interfacing ICs for piezoresistive sensors, namely the MAX14XX series [12] and MBSTC-02 [13] respectively. But the non-dynamic compensation, high cost (of the calibration kit and the IC itself) and tedious calibration process remained the major disadvantages. There are also some very unique compensation methods have been reported like using some calibration algorithm implemented in 2μm CMOS process [14], by thermal feedback [15], using indirect readout method [16] and with some miscellaneous analog signal processing techniques [17], [18]. But all of them ignore the sensitivity variation (except [15], whose accuracy is poor) and the compatibility of MEMS process with small feature size commercial CMOS process was not addressed at all. Some algorithms are yet to be implemented in commercial CMOS process (like the compensation based on ANN algorithm [19]). In this paper a new, low cost compensation circuit has been proposed, which is implemented in 0.18μm commercial CMOS process. This circuit can dynamically compensate the nonlinear sensitivity and offset temperature dependency with accuracy comparable with digital EEPROM based methods. In this compensation scheme a variable current is used to bias the bridge instead of voltage. This modification breaks the sensor sensitivity-CMOS scaling trade-off. The sensor sensitivity is controlled by varying the bridge bias current (I b ) and a feedback loop keeps the bridge bias voltage (V b ) fixed to a desired value, which is to be set externally. While V b is kept fixed, I b varies with temperature. The offset correction circuit determines the offset at the operational temperature. The accuracy of this circuit is limited by a theoretical limitation. This accuracy has been improved using a set of 25 external trimming resistances. The calculated offset is subtracted from the original input signal at the main amplifier after first stage. In this system, no separate temperature sensor has been implemented to measure the operational temperature; rather various intermediate sensor voltages are judiciously used to extract the temperature information. III. 3. B UILDING B LOCKS The accelerometer structure consists of eight boron- diffused piezoresistors (PZRs), four flexures, a proof mass and a supporting frame. The flexures support the proof mass. On each flexure, two PZRs are located at maximum stress regions, one near the proof mass and other near the frame [20]. The isometric view with wiring connections of the accelerometer is shown in Fig. 3. The accelerometer can sense acceleration along z axis (Fig.3), which is defined as on-axis and the other two axes are defined as off-axis (x and y axis). These PZRs are connected to form a Wheatstone bridge for sensing the acceleration. Change in different resistances for z, x and y axis acceleration are shown in Fig.4 (a), (b), (c) respectively. Each PZR is designed to have a nominal resistance of 1.5k Ω and a PZR sensitivity of 2 Ω /g. To obtain 1mv/g sensitivity at 27oC, I is set at 250μA. A single stage, folded cascode OpAmp with NMOS input pair and auto-zero functionality (shown in Fig. 5 [21]) is used for each of the four stages of each branch. In storing phase of the auto-zero clock (when C az is high), the input terminals of the OpAmp are shorted to the input common mode voltage and the output offset voltage is stored in the capacitors C1 and C2. In correcting phase (when C az is low), the input terminals are connected to the signal and those two capacitors are disconnected from respective outputs. Transistors M3 and M4 adjust the current through M7 and M8 depending on the magnitude and polarity of output offset ...

Context 2

... completely analog and generic interface circuit that can solve all the above mentioned problems and makes it easier to integrate the MEMS sensor with commercially available CMOS process as a low cost smart MEMS sensor. Section II discusses the architecture of the sensor and interfacing circuit. Building blocks of the smart MEMS sensor are discussed in section III. In section IV, simulation results are given, followed by conclusion in section V. II. A RCHITECTURE The smart MEMS implemented in this paper consists of a MEMS sensor and an interfacing circuit. The sensor is a uni- axial, quad beam, piezoresistive accelerometer, designed for ±13g acceleration range and low off-axis sensitivity. The total interfacing circuit can be divided into two parts. One part consists of a low offset, low noise, variable gain, instrumentation amplifier along with a peak detector and a gain controlling circuit. The other part consists of a novel circuit for sensor sensitivity and offset temperature compensation. Without any separate temperature sensing unit, this circuit can dynamically compensate the nonlinear temperature dependency of sensor sensitivity and offset. Timing control block generates all clock signals and a fail-safe Triple Modular Redundant (TMR) bias generator block generates all bias voltages and currents. Overall block diagram of the main amplifier and the sensitivity-offset compensation circuit have been shown in Fig.1 and Fig.2 respectively. There are broadly three types of circuit topologies for dynamic reduction of offset and 1/f noise [3], [4]. It is possible to combine two or more of these topologies to obtain a optimized result. Table 1 shows a comparison between these topologies. There are various hybrid topologies reported for low offset and 1/f noise, (as low as 100nV input offset [5]) but all of them have either very low system bandwidth or low dynamic range [6], [7], [8] . In this work the main amplifier is a combination of two well known low offset, low noise topologies, namely chopper and ping-pong auto-zero. Each of the two parallel branches of the main amplifier is auto zeroed and the whole amplifier is put inside a pair of choppers. Chopping frequency is 100kHz (1/f noise corner frequency of the amplifier is around 1kHz). The auto-zero technique prevents the amplifier from becoming saturated due to its own offset, as the input offset of each amplifier will be multiplied by the close loop gain of that amplifier. This hybrid implementation lifts the severe bandwidth limitation of nested chopper amplifier and ping- pong auto-zero provides continuous time output (no loss of information).Each branch consists of four cascaded amplifiers. First amplifier is a fixed gain OpAmp and the rest are of variable gain. The input signal is modulated by the input chopper (C ch is the chopper clock in Fig. 1) and then amplified by cascaded OpAmps. The output chopper demodulates the signal back to its original frequency but modulates the offset and the 1/f noise around 100kHz. The auto-zero switches are operating at 12.5kHz (C az in Fig. 1). Afterwards two types of Low Pass Filters (LPFs) are used to filter out the modulated offset and 1/f noise. First LPF is a second order, differential-in-differential-out, continuous time (using on chip lumped resistances and capacitances) filter with cutoff frequency 10kHz. which is followed by three stages of second order, differential-in-differential-out, variable cut-off frequency Switched Capacitor LPF (SCLPF). The filtered output is fed to a peak detector circuit (PD). Subsequently, two bit digital signal is generated by PD and a Finite State Machine (FSM) is designed to change the gain of the amplifier. The amplifier is designed for a bandwidth up to 5kHz, and a maximum gain of 104dB, with a dynamic range of 84dB. In the 1980’s, temperature dependency of sensor sensitivity and offset were corrected either by special devices whose temperature characteristics are complimentary to that of the original sensor [9] or by modulating the bridge supply [10]. But the compensation was not dynamic and accuracy was very poor. In the 1990’s, some papers reported the use of a second passive bridge for compensation [11]. As the piezoresistivity is a coupled function of stress and temperature, such techniques had the similar draw backs as those of the 1980’s. Later digital techniques were used to store sensitivity and offset data and then compensate the sensor. MAXIM and Microbridge Technologies Inc. came up with highly accurate interfacing ICs for piezoresistive sensors, namely the MAX14XX series [12] and MBSTC-02 [13] respectively. But the non-dynamic compensation, high cost (of the calibration kit and the IC itself) and tedious calibration process remained the major disadvantages. There are also some very unique compensation methods have been reported like using some calibration algorithm implemented in 2μm CMOS process [14], by thermal feedback [15], using indirect readout method [16] and with some miscellaneous analog signal processing techniques [17], [18]. But all of them ignore the sensitivity variation (except [15], whose accuracy is poor) and the compatibility of MEMS process with small feature size commercial CMOS process was not addressed at all. Some algorithms are yet to be implemented in commercial CMOS process (like the compensation based on ANN algorithm [19]). In this paper a new, low cost compensation circuit has been proposed, which is implemented in 0.18μm commercial CMOS process. This circuit can dynamically compensate the nonlinear sensitivity and offset temperature dependency with accuracy comparable with digital EEPROM based methods. In this compensation scheme a variable current is used to bias the bridge instead of voltage. This modification breaks the sensor sensitivity-CMOS scaling trade-off. The sensor sensitivity is controlled by varying the bridge bias current (I b ) and a feedback loop keeps the bridge bias voltage (V b ) fixed to a desired value, which is to be set externally. While V b is kept fixed, I b varies with temperature. The offset correction circuit determines the offset at the operational temperature. The accuracy of this circuit is limited by a theoretical limitation. This accuracy has been improved using a set of 25 external trimming resistances. The calculated offset is subtracted from the original input signal at the main amplifier after first stage. In this system, no separate temperature sensor has been implemented to measure the operational temperature; rather various intermediate sensor voltages are judiciously used to extract the temperature information. III. 3. B UILDING B LOCKS The accelerometer structure consists of eight boron- diffused piezoresistors (PZRs), four flexures, a proof mass and a supporting frame. The flexures support the proof mass. On each flexure, two PZRs are located at maximum stress regions, one near the proof mass and other near the frame [20]. The isometric view with wiring connections of the accelerometer is shown in Fig. 3. The accelerometer can sense acceleration along z axis (Fig.3), which is defined as on-axis and the other two axes are defined as off-axis (x and y axis). These PZRs are connected to form a Wheatstone bridge for sensing the acceleration. Change in different resistances for z, x and y axis acceleration are shown in Fig.4 (a), (b), (c) respectively. Each PZR is designed to have a nominal resistance of 1.5k Ω and a PZR sensitivity of 2 Ω /g. To obtain 1mv/g sensitivity at 27oC, I is set at 250μA. A single stage, folded cascode OpAmp with NMOS input pair and auto-zero functionality (shown in Fig. 5 [21]) is used for each of the four stages of each branch. In storing phase of the auto-zero clock (when C az is high), the input terminals of the OpAmp are shorted to the input common mode voltage and the output offset voltage is stored in the capacitors C1 and C2. In correcting phase (when C az is low), the input terminals are connected to the signal and those two capacitors are disconnected from respective outputs. Transistors M3 and M4 adjust the current through M7 and M8 depending on the magnitude and polarity of output offset ...