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Magnetic flip-flop: a volatile D-latch; b STT-MRAM with sense amplifier circuit; c STT writing circuit; d self-enable control circuit; e power gating cell using header switch
Source publication
Presently, leakage in a complementary metal oxide semiconductor (CMOS) increases due to high static power dissipation during reading and writing operations. Spin transfer torque magnetic random access memory is seen as the most reassuring non-volatile memory structure to overcome the current problem of static power dissipation. In conventional tech...
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Citations
... MRAM is a non-volatile random-access memory that uses electrons spin to store information. Spin Transfer Torque MRAM (STT-MRAM) is a promising non-volatile memory candidate with fast speed, infinite endurance, and excellent scalability [47,53]. There are two kinds of MRAM based on the MTJ reading method. ...
High leakage power consumption has become one of the main concerns of data security protection with CMOS device scaling. Spintronic technology is one of the efficient solutions to control circuit leakage power consumption by benefiting from its non-volatility property. Spintronic devices such as magnetic tunnel junctions (MTJs) are also compatible with CMOS transistors and suitable for designing hybrid MTJ/CMOS circuits. Hybrid MTJ/CMOS circuits can be used in many applications, such as logic-in-memory (LiM) and high-security structures. These circuits demonstrate enhanced data security compared to CMOS-based circuits by leveraging their non-volatile feature, making information leakage and data access more challenging. However, these circuits are not completely immune to attacks, and information can be revealed by potent power analysis attacks such as differential power analysis (DPA) and correlation power analysis (CPA). This paper investigates the resistance to side-channel attacks, especially DPA and CPA, for the magnetoresistive RAM (MRAM) and hybrid MTJ/CMOS AND, OR, XOR gates, hybrid MTJ/CMOS full-adder, and multiplexer circuits. Comprehensive post-layout simulation results using 40 nm TSMC CMOS technology, Monte-Carlo results, and values of normalized energy deviation (NED), normalized standard deviation (NSD)), and normalized power deviation (NPD) of PCSA-based MRAM indicate that the power consumption pattern remains constant in circuits with symmetrical structures in the reading phase even in the presence of inevitable process variation, so these circuits are resilient to power attacks and are competent for use in high-security applications such as hardware implementation of encryption algorithms.
... To address this issue, utilizing nonvolatile flip-flops (NVFFs) has been introduced for data retention in power-gated blocks [22]. Among the various NVFF structures, magnetic tunnel junction (MTJ)-based NVFF is the most promising candidate, thanks to the unique features of MTJ such as nonvolatility and full compatibility with the current fabrication processes [5,9,24,26]. ...
Recently, nonvolatile spintronic memory elements have drawn a lot of attention for designing nanoscale integrated circuit design due to their several advantages such as near-zero static power, high endurance, good scalability, and compatibility with the current process technologies. In this paper, a high-speed and low-power spintronic-based nonvolatile level converter flip-flop (NVLCFF) is proposed. This efficient design facilitates the use of power gating and dual-supply techniques simultaneously for ultra-energy-efficient integrated circuits. The proposed NVLCFF uses the spin Hall effect-assisted spin-transfer torque magnetic tunnel junction (SHE-assisted STT-MTJ) to provide nonvolatile data storage. Furthermore, a new voltage level converter is presented to perform voltage level conversion in the proposed NVLCFF. Elimination of the contention condition, using one reconfigurable MTJ, and no static voltage division in the proposed design lead to considerably higher speed and lower power. The 7-nm FinFET, as one of the leading industrial technologies, is utilized to design the peripheral circuity. The HSPICE simulation results show on average, 64%, 62%, and 35% improvements regarding the power dissipation, backup energy, and restore energy as compared to the other NVLCFFs. Furthermore, comprehensive Monte Carlo simulations demonstrate the robustness of the proposed design in the presence of process variations.
... Different switching methods, such as field-induced magnetic switching (FIMS), thermally assisted switching (TAS) and spin torque transfer (STT), have been proposed in recent years [34]. However, the spin torque transfer (STT) method has become more conventional due to its simplicity and higher performance, compared to the other approaches [30]. In STT MTJ, a bidirectional current is injected through the device. ...
... According to the magnetization anisotropy of the ferromagnetic layers, the MTJs can be categorized into the perpendicular anisotropy MTJ (PMTJ) and in-plane anisotropy MTJ (IMTJ). As the PMTJ device has a smaller switching critical current with the same thermal stability, it is more suitable for low-power design [2,30,31]. Therefore, in this work, PMTJ is used as the nonvolatile storage device. The switching critical current of PMTJ can be given as where α is the Gilbert damping constant, μ 0 is the vacuum permeability, e is the electron charge, γ is the gyromagnetic ratio, μ B is the Bohr magneton, p is the spin polarization, V R is the reference layer volume, M s is the saturation magnetization and H k−P is the perpendicular anisotropy fields [34]. ...
... As the MTJ write process can be performed with different approaches and technologies, different types of NVFFs have already been proposed. In [30], an innovative methodology for designing low-power magnetic flip-flops with self-time logical writing based on the STT switching method was presented. This design is composed of three components including low-swing conditional capture edge-trigged flip-flop, self-time logical writing circuit and coarse-grain method-based power gating circuit. ...
Power dissipation has become a major concern in nanoscale integrated circuits. The power gating and dual-supply design methods are among the most effective approaches for reducing the static and dynamic power consumptions. However, these methods require efficient data retention and voltage level conversion. In this paper, a nonvolatile level converter flip-flop (NVLCFF) is proposed to be used in ultra-low-power integrated circuits. Our proposed NVLCFF employs the magnetic tunnel junction (MTJ) for data retention. Spin transfer torque along with the spin Hall effect is used for reconfiguring the MTJs. The peripheral circuitry is designed using 7-nm FinFET as one of the leading industrial technologies. Furthermore, to facilitate the use of the dual-supply approach, voltage level conversion is performed in the structure of the proposed NVLCFF. According to the HSPICE simulations, the power consumption, backup energy and restore energy of the proposed circuit are on average 59%, 48% and 92% lower than the other NVLCFFs based on the previous nonvolatile flip-flops with different MTJ structures. Furthermore, the comprehensive Monte Carlo simulations indicate the robustness of the proposed design in the presence of major MTJ and FinFET process variations as compared to the previous designs.
To adapt to varied working situations, the latest biomedical imaging applications require low energy consumption, high performance, and extensive energy-performance scalability. State-of-the-art electronics with higher sensitivity, higher counting rate, and finer time resolution are required to create higher precision, higher temporal resolution, and maximum contrast biomedical images. In recent days, the system’s power consumption is important critically in modern VLSI circuits particularly for the low power application. In order to decrease the power, a power optimization technique must be used at various design levels. The low power use of logic cells is a proficient technique for decreasing the circuit level power. Dual Feedback edge triggered Flip Flop (DFETFF) is considered for biomedical imaging applications in the proposed system. Initially, the high dynamic range voltage is given as input signal. The comparator output is then retried at the comparator end. The integration capacitor is employed for storing remaining voltage signal. The comparator voltage is then given to the capacitor reset block. In the proposed work, a capacitor-reset block that employs clock signal takes up a dual-feedbackedge-triggered Flip-flop as an alternative of a conventional type for reducing the final output signals errors. Dual feedback loops assure that feedback loops do not tri-state at the time of SET restoration, a scheme that could lead to SEUs in latches if a single delay component and a single feedback loop are used. In digital system, Clock gating is a competent method of lessening the overall consumption of power along with deactivating the clock signal selectively and is useful for controlling the usage of clock signal asynchronously in reference to input-signal current. The integration-control (V int ) signal is employed in controlling the integration time. On the termination of integration, the signal level phase is kept, also similar one is send to arrangement all through read period. As a result, the simulation was carried out after the design layout and the estimations of performance were made and are compared with traditional approaches to prove the proposed mechanism effectiveness for future biomedical applications.
This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18 transistors with a single‐phase clock and mixed topology. This design has lowest complexity, so flip‐flop basically focuses on the performance issue such as delay (TCQ) and average power consumption and compared with the other existing logic structured flip‐flops. The proposed circuit is implemented at 65‐nm Complementary Metal‐Oxide Semiconductor (CMOS), and 18‐nm finFET technology node using cadence virtuoso. The proposed flip‐flop architecture have outperformed transmission gate flip‐flop (TGFF) in terms of power (i.e., 74.52%). It is also showing improvement in terms of power as compared to 18‐transistor single‐phase clocking (18TSPC). This work also enhances the speed by reducing the delay minimum of 11.28% and PDP minimum of 37.18%. By using adaptive pass transistors topology to construct flip‐flop, the total area of the proposed flip‐flop reduces by a minimum of 4.78% with respect to 18TSPC, and also with the other flip‐flops reported in this paper. The proposed circuit can work properly within the frequency range up to 2‐GHz clock frequency. Monte Carlo simulations of Power and C to Q delay have been performed for 1000 samples. The proposed flip‐flop design has the lowest complexity, so flip‐flop basically focuses on the performance issue such as average power consumption and delay (TCQ), and compared with the other existing logic structured flip‐flops. This novel master slave (MS) flip‐flop design achieved using only 18 transistors with a single‐phase clock and mixed topology.
Purpose
Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.
Design/methodology/approach
The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.
Findings
A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.
Originality/value
Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.
