Fig 1 - uploaded by Shyam Akashe
Content may be subject to copyright.
Source publication
The various analysis are established more on arithmetic circuits particularly with MUX design, this paper also explores with multiplexer to optimize the power. The CMOS transmission gate logic (TGL) is used to design a new 4:1 MUX with reduction in circuit complexity compared to conventional CMOS based multiplexer design. Based on TGL, it removes t...
Contexts in source publication
Context 1
... two or more different digital signals. Of course, only one signal at a time can be placed on the one line. What is required is a device that will allow us to select, at different instants, the signal we wish to place on this common line. Such a circuit is referred to as Multiplexer. The graphical symbol and truth table of 4:1 MUX are shown in Fig. 1a, b, respec- tively. A multiplexer performs the function of selecting the input on any one of 'n' input lines and feeding this input to one output ...
Context 2
... diagram of the output signal at a data rate of 200 Gb/s. The measured eye diagram is shown in Fig. 10. The rise and fall time for the simulation is 100 fs. The MUX can operate well up to 200 Gb/s. Transistors are reduced to great extent, so that the overall area is minimized. The innovation ranges of many process and environment parameters will increase profoundly, results in strength of circuit which is becoming a key aspect in ...
Similar publications
In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of D3L family structure is presented. Performance of the circuit is evaluated and presented at different simulation corners. The results show that, compared with its dynamic version, the proposed circuit has lower power consumption and higher speed. Latency of the di...
An efficient power dissipation with Adiabatic logic using 2 phase adiabatic static CMOS logic (2PASCL) has been presented. In this research work adiabatic logic is mainly used to minimize the energy loss during the operation of the circuit. The Adiabatic circuits are low power circuits, which performs the "Reversible Logic" to conserve energy and i...
This work describes a novel integration strategy that aims at bringing adiabatic computation to large scale integration. The proposed design solution, built upon logic primitives packed into regular arrays, the Quasi-Adiabatic-Logic-Arrays (QALAs), is well suited not just for today’s silicon transistors but also for emerging devices. QALAs are inde...
Abstract: Reduction of propagation delay is very important for high speed applications. This paper gives an idea about the delay
reduction on divided-by-4/5 counter. The delay is reduced by domino logic. Dynamic domino logic circuits are widely used in advanced
digital Very Large Scale Integration (VLSI) circuits because it is uncomplicated to impl...
Citations
... As a more powerful routing example two adjacent CS-RFETs were also combined as a 2:1 multiplexer (MUX) in a transmission gateconfiguration as shown in Fig. 4 . A typical MUX is a building block for the arithmetic circuits to route inputs to output in the data path, such as network switches and processors [33] . In this specific example, one of the interconnected wires and the corresponding control gate is left open for both adjacent transistors. ...
... However, PMOS provides a strong 1 at the same time, thereby maintaining the output level. Similarly, at low input, the PMOS produces a weak 0 but NMOS supplies a strong 0 at the output [11]. TG configuration is used to isolate the components and signals/data from being transmitted to the other nodes without using any other hardware. ...
This paper highlights a comparative analysis of eight diverse techniques for 2 to 1 multiplexer implementation. The functionality is identical but significant differences in consumed power and propagation delay are observed, but diversity is achieved in terms of dynamic power consumption and delay. This paper is aimed at enabling the designer to pick out the best fit structure for a specific application in keeping with their design requirement. The multiplexers are designed at 90 nm technology node and simulated at a supply voltage of 1 V.
... Therefore, alternative technologies for silicon transistors are being explored. One of the suitable candidates for replacing CMOS technology is the CNTFET [12]. Advantages such as ballistic transmissions, high mobility, and low power consumption for CNTFET are the main reasons of much research to apply to electronic circuits [5]. ...
... This unique feature makes them quite suitable for designing logical circuits [4]. Diameter of the CNT is calculated according to the following equation [12]: ...
Using multi-valued logic (MVL) can reduce the chip area and connections which have direct effect on power consumption. Recently, according to the high ability of nanotechnology in designing MVL, some researchers have focused on this advanced approach. In this paper, primarily, a new design of quaternary multiplexer 4:1 with carbon nanotube field-effect transistors (CNFETs) is proposed. Afterward, quaternary successor, quaternary predecessor, and quaternary second level successor (quaternary second level predecessor) cells are, for the first time, introduced based on CNTFETs. All of the above-mentioned designs are applied to quaternary half adder and quaternary full adder circuits. To approve the designs, the performance is simulated by HSPICE simulator for 32-nm technology with the Stanford compact SPICE model for CNFETs. The results of simulation represent the improved PDP by 67.14% compared to the best current techniques in the literature. All of the proposed designs are evaluated under various operation conditions such as drive ability, fabrication tolerance, and different supply voltages, confirming the performance of proposed circuits.
... It can be seen that, the chip area and power dissipation of the proposed design (M2, 45nm) is the lowest among all MUXes capable of stand − alone functionality (ie, with two embedded inverters). The work in [13], although impressive, doesn't incorporate the inverters in its design. On emulating (and improving upon) their techniques, we fabricated the layout M n depicted in Fig. 8. ...
... On emulating (and improving upon) their techniques, we fabricated the layout M n depicted in Fig. 8. It was created using 45nm foundry and occupied an area of 2.345 µm 2 , less than half when compared to [13]. However, the latter's maximum throughput is still four times than this work. ...
... This anomaly can be explained by the absence of inverters, and consequently, the corresponding V dd and V ss sources; hence the power dissipation is negligible enough to be ignored by the simulation software. This would also explain the extremely low dissipation values in [13]. Another implication from the find is that the major power consumption in a MUX is due to the inverters, and their absence would preclude the formation of a MUX with stand-alone functionality. ...
... Exploration of low power logic designs within the analysis however has mainly focused on specific logic cell, namely Multiplexers, utilized in arithmetic circuits. At higher frequency the CMOS logic will operate continuously with low power consumption [4] [5]. The various methods are widely used for reducing power dissipation in circuits, reducing switching activities, supply voltages and load capacitances [6] [7]. ...
The fabrication of integrated circuits (ICs) employing two-dimensional (2D) materials is a major goal of semiconductor industry for the next decade, as it may allow the extension of the Moore’s law, aids in in-memory computing and enables the fabrication of advanced devices beyond conventional complementary metal-oxide-semiconductor (CMOS) technology. However, most circuital demonstrations so far utilizing 2D materials employ methods such as mechanical exfoliation that are not up-scalable for wafer-level fabrication, and their application could achieve only simple functionalities such as logic gates. Here, we present the fabrication of a crossbar array of memristors using multilayer hexagonal boron nitride (h-BN) as dielectric, that exhibit analog bipolar resistive switching in >96% of devices, which is ideal for the implementation of multi-state memory element in most of the neural networks, edge computing and machine learning applications. Instead of only using this memristive crossbar array to solve a simple logical problem, here we go a step beyond and present the combination of this h-BN crossbar array with CMOS circuitry to implement extreme learning machine (ELM) algorithm. The CMOS circuit is used to design the encoder unit, and a h-BN crossbar array of 2D hexagonal boron nitride (h-BN) based memristors is used to implement the decoder functionality. The proposed hybrid architecture is demonstrated for complex audio, image, and other non-linear classification tasks on real-time datasets.
Using the multi-valued logic causes the reduction in interconnections, thereby leading to the reduction in chip area and interconnection power dissipation. In order to take advantage of the multi-valued logic, the structure of a mixed-radix system using multi-valued and binary logic is more suitable than that of only using the multi-valued logic; so, the design of a multi-digit converter is necessary. In this paper, first, a new efficient quaternary-to-binary converter and a binary-to-quaternary converter based on multi-threshold voltage are designed using carbon nanotube field effect transistor (CNTFET). Then, multi-digit quaternary-to-binary and binary-to-quaternary algorithms are discussed and implemented. Subsequently, these converters are used in a multi-digit quaternary adder. It is shown that, if quaternary numbers are initially converted into binary numbers and then summation is performed (by using multi-digit quaternary-to-binary and binary-to-quaternary converters), the complexity is considerably reduced, as compared with using the quaternary full adders. Also, some other applications of these converters are discussed. The simulation results using the Stanford 32-nm CNTFET model in the HSPICE software at 0.9 V indicate the correct operation and the high performance of the proposed designs.
