Figure - available from: IET Computers & Digital Techniques
This content is subject to copyright. Terms and conditions apply.
![MPEG4 decoder block diagram, with communication BW annotated (in MB/s) and its mapping onto mesh topology [33], and experiment results
(a) MPEG4 decoder block diagram, (b) Mapping onto mesh topology, (c) Average packet latency for VOPD traffic pattern](profile/Amin-Mehranzadeh/publication/331713988/figure/fig15/AS:11431281178991279@1691144719937/MPEG4-decoder-block-diagram-with-communication-BW-annotated-in-MB-s-and-its-mapping.png)
MPEG4 decoder block diagram, with communication BW annotated (in MB/s) and its mapping onto mesh topology [33], and experiment results (a) MPEG4 decoder block diagram, (b) Mapping onto mesh topology, (c) Average packet latency for VOPD traffic pattern
Source publication
Selection strategy is an essential part of an adaptive routing algorithm that influences the performance of the networks-on-chip (NoC). A selection strategy is used for selecting the best output channel from the available channels according to the network status. This study presents a new output selection strategy called destination intensity and c...
Similar publications
The network on chip (NoC) used in the AI chip is required to be able to deliver data to multiple destination endpoints simultaneously. The existing solutions, such as hierarchial mesh (HMESH) and FATTREE all modify the connection between routers to achieve multicasting. Although this method can achieve delivering data to multiple destination endpoi...
In multi-processor system-on-chips, on-chip interconnection plays a significant role. The type of on-chip architecture being used in an application decides the performance of that application. Hence, a quick and versatile network-on-Chip (NoC) simulator, particularly for the larger designs, is essential to explore and find the best suitable NoC con...
Citations
... The research in [17] proposes an approach for computing the end-to-end delay bound of individual variable bitrate flows in a First Input First Output (FIFO) multiplexer with aggregate scheduling under weighted round-robin (WRR) policy. The authors use network calculus to derive per-flow end-to-end equivalent service curves to compute the least upper delay bounds (LUDBs) of individual flows. ...
... Also, a global congestion aware method called DCA is used to give priority to an input channel according to the destination. 2016 [17] Using network calculus to derive per-flow end-to-end equivalent service curves to compute the least upper delay bounds (LUDBs) of individual flows. They optimize the weights in WRR policy to minimize the LUDBs while satisfying performance constraints. ...
The Network-on-Chip (NoC) is a communication infrastructure designed to integrate various components of a System-on-Chip (SoC) and connect multi-core processors. In on-chip networks, routing is a process that determines how a data packet should move from the source node to the destination node. Essentially, a routing algorithm configures the internal connections of a switch to establish communication towards the destination node by examining the source, destination and the current node addresses. After routing, multiple input channels may simultaneously request access to an output channel based on the routing results. In such cases, an arbitration strategy needs to prioritize access to the output channel for the requesting input channels. This research presents an arbitration strategy called HTPA (Hybrid Traffic Pattern-Aware arbitration) that utilizes local and global information. HTPA also uses a hybrid arbitration scheme consisting of a simple arbitration and a complex switch arbitration. Additionally, it uses age-related techniques to increase the fairness of arbitration and prevent starvation. The proposed method considers certain priorities for accessing output channels based on the distance to the destination, the number of available paths from the current node to the destination, and the traffic intensity parameter. Evaluations were conducted under uniform, transient, hot spot, and MPEG4 traffic patterns and the proposed method demonstrated a reduction in average packet delay compared to RoundRobin, CAIS, and DTIS methods by 79.46%, 71.35%, and 19.91%, respectively, across various traffic patterns.
... For example, there are tens, or hundreds of cores in an SoC chip, and the interconnection distance and electric resistance can require multiple clock cycles for a communication pair between two cores in the SoC chip. To meet the need for new generation system designs, Network-on-Chip (NoC) [3,4] was proposed and had continued to be the focus of all people who work to enhance the performance of on-chip communications [5][6][7][8][9][10]. ...
... For example, Melo et al. [5] analyzed the router behavior for detecting signal upset to minimize error propagations, and Tang et al. [19] implemented a congestion avoidance method for NoC, based on the speculative reservation of network resources. Recently, Mehranzadeh et al. [6] designed a congestion-aware output selection strategy based on calculations of congestion levels of neighboring nodes, and Giroudot et al. [7] realized a buffer-aware worst-case timing analysis of wormhole routers with different buffer sizes when consecutive-packet queuing occurs. Especially, a network-cognitive traffic control mechanism for integrated congestion control and flow control was proposed in [20]. ...
A self-reconfigurable Network-on-Chip (NoC) architecture that supports anticipative Quality of Service (QoS) control with penetrative switch ability is proposed to enhance the performance of bidirectional-channel NoC communication while supporting prioritized packet transmission services. The anticipative QoS control not only allows each communication channel to be dynamically self-configured to transmit flits in either direction for a better channel utilization of on-chip hardware resources, but also enhances the latency performance for QoS services. The proposed anticipative control is based on penetratingly observing channel direction requests of routers that is two hops away from the current one. The added ability enables a router to allocate high-priority packets to a dedicated virtual channel and then rapidly bypass it to the next destination router. The provided flexibility of packet switch promises better channel bandwidth utilization, lower packet delivery latency, and furthermore guarantees the high-priority packets being served with a better QoS. Accordingly, in this paper, an enhanced NoC architecture supporting the hybrid anticipative QoS, penetrative switch, and bidirectional-channel control, namely Anticipative QoS Bidirectional-channel NoC (AQ-BiNoC) is presented. Tested with cycle-accurate synthetic traffic patterns, significant performance enhancement has been observed when the proposed AQ-BiNoC architecture is compared against conventional NoC designs.
... 13 They employ local and nonlocal information to provide a more accurate vision of the network. 23 However, since DAR estimates the delay for all the network nodes, it introduces a long latency that degrades the routing's performance. The DBAR, on the other hand, only checks the congestion condition along a single dimension (i.e., row or column) and, thus, has an incomprehensive view of the network conditions. ...
Given the advantages of network‐on‐chips (NoCs), they are rapidly improving to replace other forms of System‐on‐Chip (SoC) designs. Although various factors improve the NoC's performance, many challenges should be addressed when designing an NoC, one of which is congestion and its impacts on performance and efficiency. Hence, numerous routing algorithms have been proposed that contemplate the congestion influences to deal with its complexities. Nevertheless, given the significant impacts of overheads on performance and efficiency, it is crucial to consider them when designing an enhanced NoC. The proposed routing algorithm employs regional traffic information within multiple clusters and has a decent view of the traffic condition when choosing the path to the destination. Each node generates one bit of traffic information and propagates it only when the node is congested, thus preventing the information overhead. Finally, the path diversity parameter is utilized to identify the best route from the source to the destination. The proposed algorithm's results show that the number of received packets, average latency, average throughput, maximum latency, and energy consumption while using different traffic patterns are improved by 10.9%, 35.3%, 15.8%, 43%, and 15.3%, respectively.
... In another study, the researchers attempted to decrease packet latency and increase network throughput using an output selection method named DCA. One of the advantages of this method is the capability of utilizing it on any kind of topology and network of different dimensions [18]. The researchers in [19] proposed the adaptive routing method called PT-BAR which uses temperature conditions for packet routing. ...
... Outlines Features Selection strategy name [12] Locally congestion-aware Hardware overhead optimization EnPSR [18] Input selection strategy Throughput and latency improvement DCA [16] Fault-tolerant improve Higher throughput, low overhead Weighted path [15] Distribute the unicast and multicast traffic Performance improvement - ...
... Buffers must be able to save data temporarily to prevent congestion for input and output routers during the network chaos. The switch establishes the connection between input and output buffers [18,25,40]. The routing unit is responsible for running the routing algorithms. ...
Networks on chip (NoCs) are an idea for implementing multiprocessor systems that have been able to handle the communication between processing cores, inspired by computer networks. Efficient nonstop routing is one of the most significant applications of NOC. In fact, there are different routes to reach from one node to another node in these networks; therefore, there should be a function that can help to build the best route to reach the destination. In the current study, a new hybrid algorithm scored regional congestion-aware and neighbors-on-path (ScRN) is introduced to choose better output channel and thus improve NOC performance. Having utilized the ScRN algorithm, first an analyzer is used to inspect the traffic packets, and then the NoC traffic locality or nonlocality is determined based on the number of the hops. Finally, if the traffic is local, a scoring technique will choose better output channel; however, if the traffic is nonlocal, the best output channel will be chosen based on a particular parameter introduced here as well as the system status using NoP or RCA selection functions. In the end, via Nirgam simulation, the proposed approach was assessed in traffic scenarios through various selection functions. The simulation results showed that the solution was more successful in terms of delay time, throughput, and energy consumption in comparison to other solutions. It showed a reduction of 38% in packet latency, and the throughput increased by 20%. By considering these two parameters, energy consumption decreased by 10% on average.
... Network-on-chip (NoC) has been proposed as an enormously scalable solution to address the communication demands of Multi-/Manycore systems due to its reusability, scalability, and parallelism in communication infrastructure [1]. Routing method influences the performance of NoC significantly, which determines a path from a source node to destination node [2]. Routing methods of NoC are divided into deterministic routing methods, oblivious routing methods and adaptive routing methods. ...
This letter presents an oblivious and load-balanced routing (OLBR) method without virtual channels for 2D mesh Network-on-chip (NoC). To balance the traffic load of network and avoid deadlock, OLBR divides network nodes into two regions, one region contains the nodes of east and west sides of NoC, in which packets are routed by odd-even turn rule with Y direction preference (OE-YX), and the remaining nodes are divided to the other region, in which packets are routed by odd-even turn rule with alterable priority arbitration (OE-APA). Simulation results show that OLBR's saturation throughput can be improved than related works by 11.73% and OLBR balances the traffic load over entire network.
... The complex arbiter in the proposed input selection strategy (DTIS) selects an input channel with the higher channel congestions level (Occupy_Slots_Score). DTIS uses a new global congestion aware scheme based on destination node called DCA method (DCA_Score) [20]. Also, it presents a new priority scheme based on the traffic pattern to provide quality of service requirements (Priority_Score). ...
... The DCA (Destination Congestion Awareness) is a method to distribute traffic more equally over the network based on the packet destination address [20]. The DCA by using only local information, without using any additional wires, tries to send flits to the destination nodes and helps to distribute traffic more evenly over the network. ...
... values for the current node will be updated according to the destination related part. Further details of the DCA method are presented in our previous research [20]. that the current node is located at (3,3) and it wants to grant access to one of the two requests from west and south input ports. ...
An input selection strategy is an important part of a router that is done by an arbitration process. When an output channel is requested by two or more input channels simultaneously, the best input channel will be selected by the input selection strategy. This research presents a new input selection strategy called DTIS (Destination Traffic based Input Selection). The DTIS uses local and non-local congestion information on the path to distribute traffic more evenly over the network. Also, a global congestion aware method called DCA is used to give priority to an input channel according to the destination. The simulation results prove that DTIS improves the average latency and throughput for various synthetic and real traffic patterns with acceptable overhead in terms of area consumption. The simulation results show the average delay improvements of DTIS to the CAIS and Round Robin strategies are 26% and 77%, respectively.
... These metrics are critically impacted by network congestions due to resource contentions [13]. Therefore, contention resolution is key to avoid network congestions [7,9]. Assuming the routing scheme is both deadlock-free and livelock-free, contention resolution relies on the efficient utilization of available network resources to enhance overall performance [13]. ...
... For congestion control, adaptive routing schemes [14,15], can be used to forward packets around the contentious regions. In NoCs, most congestion control schemes select profitable routing paths by monitoring some forms of buffer fill level [7,9,10,[16][17][18][19][20]. NoC link-layer (node-to-node) flow control schemes [6,8,[20][21][22], are developed to prevent buffers overfill between neighboring nodes. ...
... For example, Melo et al. [5] analyzed the router behavior for detecting signal upset in order to minimize error propagations, Chang et al. [6] provided a contention prediction scheme for better adaptive routing path decisions, and Tang et al. [7] implemented a congestion avoidance method for NoC, based on the speculative reservation of network resource that was proposed by Jiang et al. [8]. Recently, Mehranzadeh et al. [9], designed a congestion-aware output selection strategy based on calculations of congestion levels of neighboring nodes, Giroudot et al. [10], realized a buffer-aware worst-case timing analysis of wormhole routers with different buffer sizes when consecutive-packet queuing occurs. ...
A novel network-on-chip (NoC) integrated congestion control and flow control scheme, called Network-Cognitive Traffic Control (NCogn.TC), is proposed. This scheme is cognizant of the fluidity levels in on-chip router buffers and it uses this measurement to prioritize the forwarding of flits in the buffers. This preferential forwarding policy is based on the observation that flits with higher levels of fluidity are likely to arrive at their destinations faster, because they may require fewer routing steps. By giving higher priority to forward flits in high-fluidity buffers, scarce buffer resources may be freed-up sooner in order to relieve on-going traffic congestion. In this work, a buffer cognition monitor is developed to rapidly estimate the buffer fluidity level. An integrated congestion control and flow control algorithm is proposed based on the estimated buffer fluidity level. Tested with both synthetic traffic patterns as well as industry benchmark traffic patterns, significant performance enhancement has been observed when the proposed Network-Cognitive Traffic Control is compared against conventional traffic control algorithms that only monitor the buffer fill level.
Managing Multi-Processor Systems-on-Chip (MPSoCs) is becoming increasingly complex as demands for advanced capabilities rise. This complexity is due to the involvement of more processing elements and resources, leading to a higher degree of heterogeneity throughout the system. Over time, management schemes have evolved from simple to autonomous systems with continuous control and monitoring of various parameters such as power distribution, thermal events, fault tolerance, and system security. Autonomous management integrates self-awareness into the system, making it aware of its environment, behavior, and objectives. Self-Aware Cyber-Physical Systems-on-Chip (SA-CPSoCs) have emerged as a concept to achieve highly autonomous management. Communication infrastructure is also vital to SoCs, and Software-Defined Networks-on-Chip (SDNoCs) can serve as a base structure for self-aware systems-on-chip. This paper presents a survey of the evolution of MPSoC management over the last two decades, categorizing research works according to their objectives and improvements. It also discusses the characteristics and properties of SA-CPSoCs and explains why SDNoCs are crucial for these systems.
Networks on chips (NoCs) are a concept inspired by computer networks for constructing multiprocessor systems that can handle communication across processing cores. One of the most critical applications of NOC is efficient nonstop routing. Different routes exist in these networks to get from one node to another; thus, a function that can assist in determining the optimum route to the target should be available. This paper uses a new hybrid method called Scored Regional congestion aware and DICA (ScRD) to select a better output channel and increase NOC performance. After applying the ScRD algorithm, the traffic packets are examined by an analyzer, which determines if the NoC traffic is local or non-local based on the number of hops. Therefore, if the traffic is local, a scoring mechanism will select a better output channel; otherwise, the best output channel will be chosen using DICA or RCA selection functions, depending on the system state and the introduced parameter. Finally, Nirgam simulation was used to test the suggested method under various traffic conditions and selection criteria. The simulation results demonstrated that the strategy outperformed delay time, throughput, and energy consumption alternatives. It reduced packet delay by 27.10% and increased throughput by 10%. When these two factors were considered, energy consumption dropped by 6.86%. Also, the synthesis results showed that the hardware cost of the proposed approach is 1.2% lower than the two basic methods.
