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... iteratively the interference caused by MIMO. Among different equalization methods, MMSE-IC is a prominent lowcomplexity suboptimal algorithm. The use of the MMSE algorithm in iterative scheme compensates sub-optimality leading to an error-rate performance close to one achieved when using optimal high-complexity Maximum-likelihood (ML) algorithm. Fig. 1 shows the block diagram of the MIMO-OFDM receiver using MMSE-IC turbo-equalization. The architecture of the equalizer model based on MIMO MMSE-IC algorithm is influenced by flexibility parameters extracted from the following requirements: (1) the capability to support different MIMO schemes reaching to 4×4 antenna dimension, (2) the ...
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This Habilitation to supervise research presents the numerous research activities performed since 2014 targeting the development of flexible and efficient architectures for high performance embedded computing. The presented research activities aim at the realization of flexible and efficient architectures in multitude application domains such as digital communication, data-flow, neural networks, embedded machine learning and embedded vision. These research works have addressed the design and implementation of novel hardware architectures aiming to attain the emergent flexibility requirement, and the ever-increasing requirements of enhanced performance and reduced power consumption and implementation resources. The performed work has targeted the elaboration of new algorithms and hardware architectures using different design paradigms. In this context, several research works have been initiated through completed or ongoing research projects, two defended PhD theses and several Master theses. The most significant achievements are presented by grouping them in four sub-themes: (1) Flexible yet efficient architectures for applications in the digital communication domain; (2) Efficient algorithms and architectures for dataflow applications; (3) Efficient and flexible design paradigms based on emergent memristive devices and (4) Efficient implementations of machine learning algorithms. Current research activities focus on embedded computer vision and artificial intelligence with the goal of achieving efficient implementations on edge devices with low computational resources and low power budget.
Several application-specific processor design approaches have been proposed and investigated to cope with the emerging flexibility requirements jointly associated with the maximum performance efficiency and minimum implementation area and power consumption. Dynamic scheduling of a set of instructions generally leads to an overhead related to instruction decoding. To mitigate this overhead, other approaches have been proposed using static scheduling of datapath control signals. In this context, No-Instruction-Set-Computer (NISC) concept have been introduced considering that a dedicated processor to a specific application does not need an instruction set especially when it is programmed by its designers and not by its users. In this paper, the hardware architecture design of flexible NISC-based architecture design dedicated for minimum mean-squared error (MMSE) linear detection is presented. The devised design, which is used in iterative turbo-receiver, fulfills the performance requirements of emergent wireless communication standards with throughput reaching that of LTE-Advanced. FPGA hardware implementation of the detector architecture achieves a maximum throughput of 115.8 Mega Symbols per second for 2×2 and 6.4 Mega Symbols per second for 4×4 MIMO systems for an operating clock frequency of 202.67 MHz.
Applications in wireless digital communication field are becoming increasingly complex and diverse. Circuits and systems adopted in this application domain must not only consider performance and implementation constraints but also the requirement of flexibility. The combination of flexibility and the ever increasing performance requirements demands design approach that provides better ways of controlling and managing hardware resources. An application-specific instruction-set processor (ASIP) design approach is a key trend in designing flexible architectures. The ASIP concept implies dynamic scheduling of a set of instructions that generally leads to an overhead related to instruction decoding. The no-instruction-set-computer (NISC) concept has been introduced to reduce this overhead through the adoption of static scheduling. In this brief, the NISC approach is explored through a case-study design of universal demapper for multiple wireless standards. The proposed design has common main architectural choices as a state-of-the-art ASIP for comparison purpose. The obtained results illustrate a significant improvement in execution time and implementation area while using identical computational resources and supporting same flexibility parameters.
