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MDAC architecture of 16 bit pipeline ADC using CFCS

MDAC architecture of 16 bit pipeline ADC using CFCS

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Architecture of 16-bit pipeline ADC with 3.5 bits/stage
Conventional design of MDAC of 16 bit pipeline ADC
Transfer curves: a Δ > 0, b Δ < 0
Residue transfer function for the proposed 3.5 bit/stage
+4 MDAC architecture of 16 bit pipeline ADC using CFCS
CFCS calibration circuit design for multi-bit pipelined ADC architectures
Article
Full-text available
  • Dec 2018
Design of high resolution ADCs in scaled CMOS technology is challenging due to increased component mismatch, comparator offset, and finite op-amp gain error. In this work, a commutated feedback capacitor switching calibration technique has been proposed to improve the ENOB and linearity of ADCs with multi-bit pipeline architecture. During normal op...
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