Low-power, 100-kHz clock oscillator schematic, including nA current reference generator and startup circuit. Total dynamic current draw is 630 nA. 

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Context 1

... Details of the wireless battery recharger were published in [3] and are beyond the scope of this manuscript. The PMU proposed here is a collection of circuits respon- sible for controlling the overall current draw of the ASIC, as detailed in Fig. 1b. The PMU circuits are always running and set the baseline current draw of the system. The power consumption of these circuits was reduced as much as possible while maintaining acceptable performance and matching. The power consumption of other analog circuits is reduced by a digital finite state machine which turns the instrumentation circuitry on/off in a pipelined manner to minimize the active time for each stage. Because the wireless sensor is powered by a secondary cell with fairly large internal resistance, the battery voltage changes significantly with load current, in addition to the slow decrease caused by depletion of stored charge. The PMU uses a simple linear voltage regulator to reduce instrumentation circuit and clock oscillator voltage coefficient requirements. The regulator schematic is presented in Fig. 2. The regulator topology deviates from the traditional low- drop-out configuration by generating its bandgap reference from the regulated supply, V , rather than the unregulated input voltage, V BAT . This configuration provides excellent voltage regulation because the bandgap supply sensitivity is reduced by the loop gain of the regulator, but proper startup and overall stability is more difficult to achieve. A voltage divider formed by matched, long composite transistors M F1-F6 provides a feedback factor of 1⁄2 to the error amplifier; the resulting output voltage of the regulator is twice V . This circuit has potentially two undesirable operating points, a zero-current mode and a second mode in which FETs M 1-7 are in triode, and Q 3 carries a very low current. The AC- coupled startup networks provide pulses of current that over- come these modes, provided that the input supply VBAT has a ramp-up rate greater than 100 V/s [5]. The clock source for the PMU state machine is a low- power, current-limited relaxation oscillator, shown in Fig. 3. The oscillator symmetrically charges capacitor C 0 at a fixed rate of I 0 through an H-bridge switch configuration. When the differential voltage across C 0 exceeds the comparator hystere- sis threshold V TH [6], the capacitor polarity is flipped. The circuit produces a triangle wave of amplitude ±V TH across C 0 and a corresponding binary clock waveform at the comparator outputs. The oscillation period is given by 2 ⁄ 4 , where is the total loop delay from the oscillator output through C 0 . An oscillation frequency of 100 kHz was designed with C 0 = 3.4 pF, V TH = 55 mV, I 0 = 60 nA and T D of 940 ns. The charging current I is copied from the nA bias generator of Fig. 3 [7], which was designed using inversion-coefficient methodology [8] to ensure reasonable current matching. Matched devices M 1-2 , M 7-9 , and M 8-10 were biased in mod- erate inversion with inversion coefficients of 0.3. Transistors M 3 and M 4 were biased deep into weak inversion with IC = 0.03 to create a 30-nA reference current with R 1 = 230 k Ω . The common-mode level of C 0 is determined by the ratio of small-signal output resistances of M 9 and M 10 . Since NMOS devices have lower and increased junction leakage, the comparator uses a PMOS input pair and can tolerate input common-mode levels including 0V. Static differential-mode offsets caused by non-equal charge injection and comparator differential pair offset can change the clock duty cycle from the nominal 50%. Dynamic differential-mode offsets such as the comparator input-referred thermal and 1/ noise and the uncorrelated channel noise between M 9 and M 10 plus dynamic changes in T are the primary sources of oscillator jitter. The PMU state machine controls power consumption through low-duty-cycle operation of analog circuits. This is possible because of the huge speed difference between instrumentation circuitry and the required 100-Hz sampling rate for bladder pressure. The proposed PMU state machine applies power activation to individual circuits, creating a sample pipe- line in which sensed information is passed between sequential stages as charge stored on switched capacitors. Stages are switched off as sampled are acquired and conveyed to the fol- lowing stage. The PMU state machine timing diagram illu- strated in Fig. 4 shows power gating signals of Fig. 1a. Fast-settling elements, such as the piezoresistive pressure transducer and IDAC, have lower duty factors than switched- capacitor and bias circuits, which have longer warmup, step response, and settling limitations. To reduce peak current and RF interference, the FSK transmitter is separately activated for 450 μs after each sample period as determined by the adaptive-rate transmitter described in Section III. The sample rate of the pressure sensing system is 100 Hz, and the PMU state machine requires just 475 μs to acquire a sample, although some instrumentation circuits are only activated for a small fraction of this time. The time-average current consumption of individual instrumentation circuits is thus reduced to between 1.4 and 6.5 percent. The average current for the pressure sensor IC is dominated by the transmitter when the transmission rate is greater than 25 Hz, as shown in Fig. 5. The PMU, piezoresistive pressure transducer, and digital circuits dominate power consumption at lower rates. III. A CTIVITY D ETECTOR FOR A DAPTIVE T RANSMISSION R ATE C ONTROL A sample rate of 100 Hz is required to capture fast transients in bladder pressure, but a fixed, 100-Hz telemetry would account for 81% of the system current. Because bladder contractions are intermittent, significant power savings can be achieved by only transmitting “active” samples. A digital im- plementation of an activity detector designed specifically for bladder pressure signals is presented in Fig. 6a. The activity detector is based on the first and second differences of the signal [9]. When these differences are combined, the expression becomes that of a 2 nd -order FIR filter given by 1 2 . (1) Coefficients α and β can be selected such that is an in- dicator of activity. Coefficient values of -1⁄2 were chosen to create a high-pass filter with a peaking response at ⁄ 4 , unity gain at ⁄ 2 and zero DC gain. The FIR filter output is com- pared to a threshold by a magnitude comparator; if the sample is significant enough, it is transmitted. A rate control register, which sets the baseline transmission rate from 1.5 – 100 Hz, is adjusted based on the level of pressure activity. Samples are transmitted at the baseline rate even if the comparator does not indicate activity. The rate control register is incremented when the magnitude comparator de- tects activity, and is decremented at a constant rate of 40 ms. Thus, transmission rate remains high for a period of time after activity. Waveforms demonstrating this operation are shown in Fig. 6b for representative, non-voiding bladder contractions. IV. E XPERIMENTAL R ESULTS The PMU circuits ...

Context 2

... Details of the wireless battery recharger were published in [3] and are beyond the scope of this manuscript. The PMU proposed here is a collection of circuits respon- sible for controlling the overall current draw of the ASIC, as detailed in Fig. 1b. The PMU circuits are always running and set the baseline current draw of the system. The power consumption of these circuits was reduced as much as possible while maintaining acceptable performance and matching. The power consumption of other analog circuits is reduced by a digital finite state machine which turns the instrumentation circuitry on/off in a pipelined manner to minimize the active time for each stage. Because the wireless sensor is powered by a secondary cell with fairly large internal resistance, the battery voltage changes significantly with load current, in addition to the slow decrease caused by depletion of stored charge. The PMU uses a simple linear voltage regulator to reduce instrumentation circuit and clock oscillator voltage coefficient requirements. The regulator schematic is presented in Fig. 2. The regulator topology deviates from the traditional low- drop-out configuration by generating its bandgap reference from the regulated supply, V , rather than the unregulated input voltage, V BAT . This configuration provides excellent voltage regulation because the bandgap supply sensitivity is reduced by the loop gain of the regulator, but proper startup and overall stability is more difficult to achieve. A voltage divider formed by matched, long composite transistors M F1-F6 provides a feedback factor of 1⁄2 to the error amplifier; the resulting output voltage of the regulator is twice V . This circuit has potentially two undesirable operating points, a zero-current mode and a second mode in which FETs M 1-7 are in triode, and Q 3 carries a very low current. The AC- coupled startup networks provide pulses of current that over- come these modes, provided that the input supply VBAT has a ramp-up rate greater than 100 V/s [5]. The clock source for the PMU state machine is a low- power, current-limited relaxation oscillator, shown in Fig. 3. The oscillator symmetrically charges capacitor C 0 at a fixed rate of I 0 through an H-bridge switch configuration. When the differential voltage across C 0 exceeds the comparator hystere- sis threshold V TH [6], the capacitor polarity is flipped. The circuit produces a triangle wave of amplitude ±V TH across C 0 and a corresponding binary clock waveform at the comparator outputs. The oscillation period is given by 2 ⁄ 4 , where is the total loop delay from the oscillator output through C 0 . An oscillation frequency of 100 kHz was designed with C 0 = 3.4 pF, V TH = 55 mV, I 0 = 60 nA and T D of 940 ns. The charging current I is copied from the nA bias generator of Fig. 3 [7], which was designed using inversion-coefficient methodology [8] to ensure reasonable current matching. Matched devices M 1-2 , M 7-9 , and M 8-10 were biased in mod- erate inversion with inversion coefficients of 0.3. Transistors M 3 and M 4 were biased deep into weak inversion with IC = 0.03 to create a 30-nA reference current with R 1 = 230 k Ω . The common-mode level of C 0 is determined by the ratio of small-signal output resistances of M 9 and M 10 . Since NMOS devices have lower and increased junction leakage, the comparator uses a PMOS input pair and can tolerate input common-mode levels including 0V. Static differential-mode offsets caused by non-equal charge injection and comparator differential pair offset can change the clock duty cycle from the nominal 50%. Dynamic differential-mode offsets such as the comparator input-referred thermal and 1/ noise and the uncorrelated channel noise between M 9 and M 10 plus dynamic changes in T are the primary sources of oscillator jitter. The PMU state machine controls power consumption through low-duty-cycle operation of analog circuits. This is possible because of the huge speed difference between instrumentation circuitry and the required 100-Hz sampling rate for bladder pressure. The proposed PMU state machine applies power activation to individual circuits, creating a sample pipe- line in which sensed information is passed between sequential stages as charge stored on switched capacitors. Stages are switched off as sampled are acquired and conveyed to the fol- lowing stage. The PMU state machine timing diagram illu- strated in Fig. 4 shows power gating signals of Fig. 1a. Fast-settling elements, such as the piezoresistive pressure transducer and IDAC, have lower duty factors than switched- capacitor and bias circuits, which have longer warmup, step response, and settling limitations. To reduce peak current and RF interference, the FSK transmitter is separately activated for 450 μs after each sample period as determined by the adaptive-rate transmitter described in Section III. The sample rate of the pressure sensing system is 100 Hz, and the PMU state machine requires just 475 μs to acquire a sample, although some instrumentation circuits are only activated for a small fraction of this time. The time-average current consumption of individual instrumentation circuits is thus reduced to between 1.4 and 6.5 percent. The average current for the pressure sensor IC is dominated by the transmitter when the transmission rate is greater than 25 Hz, as shown in Fig. 5. The PMU, piezoresistive pressure transducer, and digital circuits dominate power consumption at lower rates. III. A CTIVITY D ETECTOR FOR A DAPTIVE T RANSMISSION R ATE C ONTROL A sample rate of 100 Hz is required to capture fast transients in bladder pressure, but a fixed, 100-Hz telemetry would account for 81% of the system current. Because bladder contractions are intermittent, significant power savings can be achieved by only transmitting “active” samples. A digital im- plementation of an activity detector designed specifically for bladder pressure signals is presented in Fig. 6a. The activity detector is based on the first and second differences of the signal [9]. When these differences are combined, the expression becomes that of a 2 nd -order FIR filter given by 1 2 . (1) Coefficients α and β can be selected such that is an in- dicator of activity. Coefficient values of -1⁄2 were chosen to create a high-pass filter with a peaking response at ⁄ 4 , unity gain at ⁄ 2 and zero DC gain. The FIR filter output is com- pared to a threshold by a magnitude comparator; if the sample is significant enough, it is transmitted. A rate control register, which sets the baseline transmission rate from 1.5 – 100 Hz, is adjusted based on the level of pressure activity. Samples are transmitted at the baseline rate even if the comparator does not indicate activity. The rate control register is incremented when the magnitude comparator de- tects activity, and is decremented at a constant rate of 40 ms. Thus, transmission rate remains high for a period of time after activity. Waveforms demonstrating this operation are shown in Fig. 6b for representative, non-voiding bladder contractions. IV. E XPERIMENTAL R ESULTS The PMU circuits were integrated with instrumentation circuits to produce a pressure sensor IC for wireless bladder pressure monitoring. The 6.25 mm 2 IC was fabricated in a 0.5- μm CMOS process and a die photo is presented in Fig. 7. The current consumption of the pressure sensor IC was measured to verify proper PMU function and to determine leakage currents not modeled through simulation. The IC draws a very low current with intermittent bursts of high peak current, when samples are acquired and transmitted. Dynamic current draw was measured by amplifying the voltage drop across a 10- Ω shunt resistor. An oscilloscope trace of the dynamic current draw is shown in Fig. 8. The minimum ...