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In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become h...
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A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To all...
Citations
... These cells delay the incident signal instead of delay approximation with phase change. Moreover, there are some other applications for below 6 GHz TTD systems for multi-standard applications, data processing, 6G, and IoT [9][10][11]. ...
A true‐time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non‐idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor‐less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non‐idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S11 and S22 parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW.
... Here we address how such heterogeneities affect the synchronization properties of such systems. Apart from component heterogeneity, the complexity introduced by time-delayed coupling, noise, and environmental effects (PVT variations) pose additional challenges to the reliable operation of these devices [20][21][22][23]. Time delay, for example, has significant effects on the collective dynamics, especially when the systems are operating at high frequencies and/or involved in long-range signal transmissions [24][25][26][27]. ...
We study synchronization in networks of delay-coupled electronic oscillators, so-called phase-locked loops (PLLs). Using a phase-model description, we study the collective dynamics of mutually coupled PLLs and report the phenomenon of heterogeneity-induced synchronization. This phenomenon refers to the observation that heterogeneity in the system's parameters can induce synchronization by stabilizing the states which are unstable without such heterogeneity. In systems where component heterogeneity can be tuned and controlled, we show how the complex collective self-organized dynamics can be guided towards synchronized states with specific operational frequencies and phase relations. This is of importance for the technical applicability of self-organized dynamics. In electrical engineering, for example, where components can be strongly heterogeneous, our theoretical framework can inform the design process for networks of spatially distributed PLLs. The results presented here are also useful in understanding the collective dynamics in ensembles of phase oscillators with time-delayed interactions, inertia, and heterogeneity.
... Nejadhasan et al. [17] have presented low noise amplifier, and mixer circuits are realized using 0.18 μm CMOS technology in the frequency range of 3.1-10.6 GHz. ...
Design of a receiver includes a Low Noise Amplifier (LNA) for astronomical radio applications. Conventionally radio telescopes are used as receivers, and antennas like a yagi antenna and orthomode transducer antenna are used to observe signals. The main aspect of LNA is to achieve sufficient Noise Figure (NF) and maximum gain at real-time applications. Previous LNA such as folded cascode LNA, Multigain LNA and multimode LNA are introduced to perform low noise amplification at the receiver side of antenna array systems. Narrowband inducer degenerated cascaded LNA design is presented in this paper. This design initially analyzed a high gain of up to 20 dB, and input matching values are found to be up to − 25db and a high reverse isolation coefficient was measured. After performing S-parameter analysis, the values are plotted in a smith chart to find the system’s stability and gain circles are plotted. The noise figure was measured and was minimized due to its inductor degeneration topology adopted in this LNA design that limits noise performance and increases gain. Proposed LNA was then evaluated with a voltage gain, power gain, and noise figure and output impedance. Evaluated values are then compared with previous methods so as to show that the proposed design has overwhelmed conventional techniques. Output load value is selected optimum as it creates an impact on the stability of LNA. The induced degeneration technique implemented in LNA design helps to increase the gain by boosting the signal input, and hence in turn, it increases overall gain performance. Similarly, while executing Narrowband inducer degenerated cascaded LNA design in CADENCE software, this LNA exhibits a minimum NF of \(2\;{\text{dB}}\; {\text{at}}\; 90\;{\text{ GHz}}\) and power gain of \(16\;{\text{dB}}\; {\text{at}}\; 90\; {\text{GHz}}\) in measurement. Thus proposed LNA design performs well for radio receiver applications.
... In the structure of the most electronic receivers, including IoT, different blocks are used to receive and process the data, also controlling and optimizing the power consumption of all blocks is important to remove the challenge [1][2][3][4]. One of the most important receiver blocks is analog to digital converter (ADC). ...
... The performance of this circuit is as follow: When CLK = low, the M 3 OUTP and OUTN are discharged to the ground potential (OUTP = OUTN = '0') and the initial value of the circuit output is determined. If CLK = high, according inputs situation to each other, the outputs are '0' or '1'. ...
In this paper, a low power and low delay comparator circuit for the IoT applications has been designed and analyzed. In the proposed comparator, two different voltage levels have been used for the preamplifier and latch sections to control delay and power consumption. To increase the difference between the outputs in the preamplifier structure, two inverter in the inputs has been used. This technique reduces the delay of the comparator outputs. In order to reduce power consumption, the latch section is designed by using SCPG transistors. The operation frequency of this circuit is 50 MHz. In this frequency, the delay and power consumption are 340 ps and 3.55 μW, respectively. The input offset voltage is about 0.6 mV. The circuit has been designed and simulated in 65 nm CMOS technology and the chip area is 230μm2.
... This paper presents an extensive study on the impact of test feature extraction, and threshold selection, on both OBT and OBIST under PVT variation at RF, using a 2.4 GHz LNA in 0.35 μm CMOS [40] as CUT, operating from a nominal V DD of 3.3 V. The process is selected for its low prototyping cost and prior usage for demonstrating novel RF circuit principles [54], [55], [56], [57]. This work extends on [40] by considering full PVT variation and not only process variation, comparing 15 OBT and OBIST approaches (as opposed to the original four), improving on the definition of the OBT figure-of-merit (FoM) and relating it to the more commonly used Test Escape (T E ) and Yield Loss (Y L ) parameters. ...
Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FoM) across PVT variation. This is done using a 2.4 GHz LNA in 0.35 lm CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape P(TE) and yield loss P(YL) of 5∙10-2 and 1.89∙10-2 respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.
There are several research possibilities as a result of the introduction of 5G wireless communication standards in India, which has increased the demand for low-noise, power-efficient, high-performance, and affordable amplifier designs for small-cell base stations. By splitting the service area into numerous small zones and reusing the limited frequency spectrum that has been allotted to them for communication, service providers can improve user density. Each front-end module (FEM) in a small cell has a corresponding transceiver.
For communication, a transceiver primarily uses two types of amplifiers: a Low Noise
Amplifier (LNA) for signal receiving and a Power Amplifier (PA) for signal transmission. LNAs amplify the signals the antenna receives while suppressing the addition of as little noise as possible. A receiver’s sensitivity and erroneous free dynamic range are determined by the LNA’s noise figure and linearity performance. For transmission, a PA instead sends an amplified signal to the antenna. The effectiveness of a FEM’s PA determines its power efficiency. Even though there are still many different amplifier designs available in the literature, research on amplifier design is still being done. The introduction of new communication standards and ongoing demands to improve a receiver’s performance in order to survive in the communication market as a service provider are the driving forces behind ongoing research on amplifier design.
Therefore, for modern 5G communication in the sub-6GHz range, we give design and fabrication insights of commercial LNA and PA designs that are low noise and powerefficient.
The following contributions to the thesis are grouped into three categories.
In parts I and II of this thesis, the amplifier MMIC was designed using 0.25-μ m GaAs
pHEMT technology. In section III, we develop and implement LNA MMIC using 0.25-μm GaN HEMT technology.
Part-I: In the first part of this thesis, we present the design and implementation of amplifier MMIC using conventional Smith chart-based impedance matching network design. We have designed a reconfigurable ultra-low noise figure low noise amplifier (LNA) in a sub-6 GHz band. The designed LNA can be reconfigured anywhere in the (1.8-5.0) GHz frequency band, with a maximum bandwidth of 600 MHz. The measured results of the LNA design exhibit state-of-the-art performance with a gain of 22 dB, Noise Figure (NF) of 0.35 dB, Output power at 3rd order intercept (OIP3) 39.4 dBm, and output power at 1dB gain compression (OP1dB) of 18.7 dBm at 1.9 GHz. Using the same method, we also present the design of a reconfigurable Low Noise Power Amplifier (LNPA) in a 1.2 - 3.8 GHz frequency band with minimum tunable bandwidth of 200 MHz at a time. The suggested LNPA design finds use in minimising cosite interference produced in 5G Multiple Input Multiple Output (MIMO) transceivers that are packed closely together. The designed amplifiers are cost-effective and compact and include on-chip inductors, DC bias and ESD protection networks.
Part-II: Other than device technology, an amplifier’s performance is mostly controlled by its matching network. We can see from the first section of this thesis that a Smith chart or onboard tuning are the only ways to get a satisfactory narrowband match. We, therefore, propose a wideband PA design with distributed impedance matching networks constructed using an analytical method in the second section of this thesis. The PA design can lessen the frequency dependence due to a good impedance match-up to band edges. We discovered that building an LNA analytically was computationally expensive because we wanted to perform multi-object optimization. For instance, while designing an LNA, we want matching networks that are concurrently optimised for high gain and low NF. We then turned to numerical methods for designing matching networks. The real frequency technique (RFT) is frequently utilised for wideband MN design. Therefore, we provide an effective Real Frequency Line-segmentation Technique (RFLT) for impedance MN design in this dissertation. By creating a wideband LNA in the 1.3 to 2.3 GHz frequency range, the suggested technique is experimentally validated. When compared to other amplifier designs found in the literature, the performance of amplifiers (PA and LNA) developed using both methodologies (analytical and numerical) is evaluated.
Part-III: Since GaN High Electron Mobility Transistor (HEMT) is recognised for their
strict performance at high power and high frequency, which enables us to do away with limiters, we also provide the design of an LNA employing GaN at the conclusion of this dissertation. Eliminating limiters enables the creation of small receiver designs with low noise figure. High Reverse Recovery Time (RRT) limits the performance of GaN LNAs when a high-power signal is applied to the LNA’s input. The RRT of an LNA can be reduced in several ways, but they all need different device technologies. We also offer a circuit-level approach to lower the RRT of an amplifier that uses GaN-only transistors as a result.
True-time delay (TTD) cells are used in timed array receivers for wideband multi-antenna topologies. TTD cells are divided into two major categories: silicon-based and non-silicon-based structures. Non-silicon-based structures have very good bandwidth but are bulky in the below 10 GHz frequency band. Silicon-based TTD cells are much more compact and better candidates for integrated circuit (IC) design. Passive and active approaches are the two ways to have a silicon-based TTD cell. Passive TTD cells are built by transmission lines (TL), artificial transmission lines (ATL), and LC ladder networks. Their power consumption is very low, and the delay bandwidth is good, but they are still bulky at low frequencies like below 5 GHz applications. Active all-pass filters as TTD cells are presented for these issues. In this chapter, we will discuss the challenges of inductor-based TTD cells. Then, inductor-less TTD cells are presented to address some of the previous structure's issues. Finally, we will talk about these structures' challenges as well. Then, the nonidealities effects on the TTD cell's performance are investigated, and the body bias technique is presented to address these issues.
In this article, we propose a matching network design algorithm based on the segmentation of the real and imaginary part of optimum source impedance curve with respect to space variable x$$ x $$ and frequency ω$$ \omega $$, respectively. The impedance curve (comprising of real and imaginary parts) is approximated as a collection of n$$ n $$ linear segments, represented by the weighted sum of n$$ n $$ semi‐infinite linear functions. Using the numerical method, optimum weight vectors that maximize transducer power gain are obtained to model the real and imaginary parts of the source impedance curve. We get the values of optimum weight vectors and the rational input impedance function for the matching network, which are then synthesized in the desired topology by a continued partial fraction. Experimentally, we validate the novelty of the proposed method by designing matching networks of a wideband custom monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) in 1.3–2.3 GHz frequency band. The measured results of the designed LNA are significantly close to the simulated results. We bias our LNA at (5 V, 150 mA) and achieve a maximum noise figure of 1.25 dB, OP1dB of 26 dBm, and an average TOI of 38 dBm. Moreover, our design of custom LNA MMIC has an integrated ESD structure while occupying only 0.32 mm² of chip area.
