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Addition is one of the fundamental arithmetic operations which are used extensively in many VLSI systems such as microprocessors and application specific DSP architectures. In this paper, the Significance Approximation Error Tolerant Carry Select Adder (SAET-CSLA) is constructed, which is efficient in terms of accuracy, power and area. While consid...
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Fast adders are constructed mainly by Carry select adders (CSLA). Area is one of the main concerns as far as any VLSI design is considered. In connection this paper enhances the performance of self checking carry select adder by introducing un footed dynamic logic based full adder cell instead of a regular CMOS based adders. The adder is constructe...
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Citations
... Jothin et al. [5] investigated, in their work, the performance of a Significance Approximation ET CSLA (SAET-CSLA) for image processing applications. The hardware complexity was minimized by using an algorithmic strength reduction method, thereby reducing the power. ...
... Although approximation computing may be accomplished in all aspects of the computer, from software to circuits, the primary focus of this research will be on ET adders [19][20][21][22][23][24][25]. Most of the work related to CSLA [2][3][4][5][6] was devoted to developing the approximation hardware and minimizing the area and power. In higher-bit adders, the propagation delay problem becomes significant in CSLA due to the presence of the RCAs and multiplexers, which is overcome by introducing modifications at the architectural level. ...
... The inferences drawn from Table 7 indicate that the average MED of the Group I adders was reduced by 99.95%, 99.93%, and 99.82% from FTFA [4], ETCSLA [5], and EMFA [6], respectively. The average MED of Group II adders was reduced by 99.92%, 99.96%, and 92.56% from FTFA [4], ETCSLA [5], and EMFA [6], respectively, whereas there was a reduction of 99.82%, 99.91%, and 81.97% in MED for Group III adders from FTFA [4], ETCSLA [5], and EMFA [6], respectively. ...
The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain optimization in power and delay, conventional CSLA is refined by substituting ripple carry adders (RCA) with the newly proposed selector unit to minimize the switching activity. The research work includes the power, area, and delay estimates of the design from synthesis using the gpdk-90 nm and gpdk-45 nm standard cell libraries. The proposed adders exhibit reduced delay, power dissipation, area, power delay product (PDP), energy delay product (EDP), and area delay product (ADP) compared to the existing approximate adders. The proposed adder is used in an image blending application. There is a significant improvement in the peak-signal-to-noise ratio (PSNR) in the blended image compared to the standard designs.
... Jothin et al., [3] have proposed the design of a 16-bit approximate adder by integrating a conventional CSLA with an Error Tolerant CSLA (ET-CSLA) to achieve considerable improvement in the accuracy of the result. The design of the approximate adder was divided into an 8-bit accurate part in which the conventional 8-bit CSLA was applied since the higher-order bits accuracy had to be preserved for correctness. ...
... In addition to area and power, the delay is also reduced by using inexact computational circuits. Based on the idea, there are varieties of approximate adders (inexact adders) [2][3][4][5][6][7][8][9], and multiplier circuits [10][11][12][13][14][15] have been described in the literature for signal processing, image processing, and deep learning applications. ...
... Approximate mirror adders [3] of various configurations and truncated adders [4] are developed and used for image compression applications to verify their performance. Other similar types of inexact adders such as Significance Approximation Error-Tolerant Carry Select Adder (SAET-CSLA) based on Approximate Full Adder (AFA) [5], Modified Full Adder-(MFA-) based High-Speed Error-Tolerant Adder (HSETA) [6], and MUX-based High-Performance Error-Tolerant Adder (HPETA) [7] are designed, and better performance is demonstrated with image blending applications. Carry Truncate Adder (CTA) [8] is deployed in Convolution Neural Network (CNN) structure for accelerating the computation of the softmax layer. ...
... GDI-based full adder for inexact computing is presented in [27]. e performance of an inexact full adder depends on its erroneous output and error distance [5][6][7]. Inexact circuit with minimal error and minimal error distance (ED) while using a smaller number of resources is challenging, and that meets the purpose of inexact computation. Our research contributes to a novel architecture that mitigates cascaded effects and addresses those challenges. ...
Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder’s design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy.
... Tab. 2 compares MED, MRED and NED value of the proposed and prior adder designs. Note from Tab. 2, that proposed adders fares better MED and MRED values compared to ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] designs. AEPA-EFA [19] design use exact full adder cell in approximate and accurate part. ...
... Tab. 2 compares MED, MRED and NED value of the proposed and prior adder designs. Note from Tab. 2, that proposed adders fares better MED and MRED values compared to ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] designs. AEPA-EFA [19] design use exact full adder cell in approximate and accurate part. ...
... Performance of the proposed and state-of the art adders in terms of total power dissipation (power), area, delay, Area-Delay Product (ADP), Power-Delay Product (PDP) and Energy-Delay Product (EDP) are shown in Tab. 3 [1], ET-CSLA [16], SAET-CSLA [16], HPETA1 [17], HPETA2 [17], SARA [18], AEPA-EFA [19], AEPA-FTFA1 [19] and AEPA-FTFA2 [19] designs respectively. Though SARA [18] implement look ahead based carry propagation in the accurate part, it shows 11.2% and 9.8% high delay compared to P-PC and P-PCER adders, thanks to the parallel carry generation logic that reduce delay of the proposed designs significantly. ...
... In ref [3] approximate subtractors proposed for various signal and image enhacement applications. Approaches in [4,5] various imprecise adders were intended for the low power circuits. ...
Approximate computing is a modern techniques for design of low power efficient arithmetic circuits for portable error resilient applications. In this work, we have proposed a Adaptive Parallel Mid-Point Filter (APMPF) architecture using proposed imprecise Max-Min Estimator (MME)targeting digital image processing. Parallel architecture for the MME can trade-off hardware at the expense of accuracy are proposed and used in the proposed APMPF. In APMPF, we use three level of sorting to estimate the mid-point of 3 x 3 window. Switching based trimmed filter is proposed for precise estimation of the selected window. Experimental Results interms of Area, Power and Delay with 90nm ASIC technology exposed that to the least, Proposed filters demonstrate 7% and 9% Area Delay Product (ADP) and Power Delay Product (PDP) reductions, respectively, compared to precise filter design.
... A number of algorithms and approaches on adder and multiplier design is proposed in the literature to optimize area, power, and delay. High speed adders for multi-bit addition include Carry Select Adder (CSLA) [12,15,16,26,34], Carry Save Adder (CSA) [20] and Carry Skip Adder(CSKA) [5,18]. Area of CSLA, CSA, and CSKA are high due to additional hardware circuitry used to improve speed. ...
... For these applications, approximate computing is a novel approach used to design lowpower, area-efficient datapath units. Approximate adders [9,12,[15][16][17]33], approximate 4:2 compressors [2,7,10,13,14] and approximate multipliers [2,10,13,14] using 4:2 compressors are proposed in the literature. Approximate adders in [9,12,15,16] maintain error within a significant limit by using approximation logic in certain least significant bits. ...
... Approximate adders [9,12,[15][16][17]33], approximate 4:2 compressors [2,7,10,13,14] and approximate multipliers [2,10,13,14] using 4:2 compressors are proposed in the literature. Approximate adders in [9,12,15,16] maintain error within a significant limit by using approximation logic in certain least significant bits. Approximate compressors in Ref [2]design 1, Ref [2]-design 2, Ref [2]-design 3 generate certain outputs directly from the input, and hence error percentage of these designs are significantly large. ...
Approximate computing is a striking approach to design area-efficient low-power datapath units for fault buoyant applications. This brief presents the design of a novel 4: 2 approximate compressor that generates no error in the carry signal. The proposed compressor is employed for partial product (PP) compression in two variants of Dadda multiplier to see its effectiveness in error-resilient image and signal processing applications. In the targeted multipliers, the approximate 4:2 compressor is used in the least n PP columns, while the exact counterpart is used in the remaining most significant columns, and hence the maximum error is precisely maintained within 2ⁿ. PP compression is performed in stages using the Wallace approach, and the final two rows of sum and carry signals are added using a ripple carry adder in the basic design. In the proposed multiplier design-2, we do not generate sum bits in the approximate part. However, the proposed error-tolerant compressor is used in appropriate columns to propagate carry to the least significant column in the exact part. Performance evaluations using Cadence Encounter with 90 nm application specific integrated circuit technology revealed that the proposed-full width (P-FW) and the proposed-truncated (P-Trun) approximate multipliers demonstrate 22.7% and 32.4% power-delay product reduction compared to the standard multiplier. Implementations of the proposed multipliers in signal and image processing applications revealed superior performance in terms of accuracy compared to prior similar approximate designs.
... Generic accuracy configurable adder (GeAr) adopting overlapping sub-adders to perform the ACA-I, ACA-II and ETAII function setting the parameters of resultant bits and numbering the previous bit for carry prediction in sub-adder (Shafique et al. 2015). The inverter gate logic can give the approximate sum output of full adder by deriving it from the accurate carry output (Jothin and Vasanthanayaki 2016). Likewise, in a CNTFET-based Inexact Full Adder (IFA-CSLA), the approximate sum output for an accurate carry output can be derived from the approximate sum output utilising inverter logic (Mehrabani et al. 2017). ...
In the modern applications there are lot of computing resources starting from Central Processing Units, Networks on Chips to Field Programmable Gate Arrays, each catering various types of operations. These factors motivate this research, to exploit 16-bit High Performance Variable Accuracy Reconfigurable Adder (HPVARA) and High Performance Error Tolerant Adder (HPETA-III) which are used extensively in many computing architectures for hybrid and error tolerant applications. The simulation based research outcome of the proposed HPVARA structure shows 13.69%, 15.95%, 9.82%, 22.53%, 13.56% improved Area Delay Product and 12.15%, 11.86%, 8.74%, 15.12%, 14.96% improved Power Delay Product with the computational outputs varying between 91.788% and 100% with the input operand pair compared to the existing ACA-I, ACA-II, GDA, VARA4 and conventional CSLA architectures. The second part of the research is focused on optimizing the design of the High Performance Error Tolerant Adder (HPETA-III). The proposed HPETA-III design performance is evaluated to offer a savings of logic gate count ranges from 268, 212, 173, 184, 196, 172, 68, 76, 60, 21 with respect to CSLA, VARA4, HSSSA, SAET-CSLA, ETCSLA, HSETA, HPETA-I, HPETA-II, CEETA, CEETA1 architectures respectively and also interesting results have been observed with reduced power, delay, PDP and ADP.
... Any improvement in the performance of this basic block leads to the improvement in various signal processing and processors. The ever-increasing demand for high-speed data processing with reasonable accuracy has led the researchers to a comparatively new field of computing, namely approximate computing (ApC) [12][13][14][15][16][17][18][19]. It has become a topic of interest for various researchers during the last decade. ...
... 14. Figure 2 shows the conventional structure of speculative PPA topology of Koggestone topology (KST) and Han-Carlson Topology (HCT). Approximate computing plays a major role in real-time applications [1,4,5,14,22]. It shows the great future ahead with the increasing demand of the modern world. ...
Approximate computing is gaining grip as a computing paradigm for computer vision, data analytics, and image/signal processing applications. In the era of real-time applications, approximate computing plays a significant role. In many computers including digital signal processors (DSP) and a microprocessor, adders are the main element for the implementation of signal processing applications and digital circuit design. The major problem for addition is the propagation delay in the carry chain. As the bit length of the input operand increases, the length of the carry chain increases. To address the carry propagation problem in digital systems, the most efficient adder architectures for VLSI implementation are classified as a parallel prefix adder (PPA) structure. In this paper, a novel methodology to implement and synthesize different adders (non-speculative and speculative) for any ASIC-based system is proposed. The proposed hybrid Han-Carlson and Kogge-stone speculative adders show improved performance (low power and delay) over the state-of-the-art approximate adders. If the approximation fails, then the proposed efficient error correction technique is activated. The proposed speculative H_C adder results in a 23.79% speed improvement over the proposed K_S adder, and 23.86% of energy is saved. The proposed architectures were synthesized for an operand bit length of 16 bits. Finally, the proposed adder is validated for an error-tolerant image processing application resulting in 41.2 dB PSNR.
... The 2-bit ripple carry adder with Cin = 1 (RCA_1) block has two numbers of FA. C1 [5] C3 [10] C6 [13] C10 [16] Cout [19] The RCA_1 has twenty six basic logic gates and eight logic delay elements on the sum computational path. The RCA_0 block has a saving of seven basic logic gates compared to the RCA_1 block. ...
... C12 [5] C13 [7] C14 [9] C15 [11] C10 [13] Sum11 [18] Sum12 [18] Sum13 [18] Sum14 [18] Sum15 [18] Cout [15] 10:5 Mux [3] Proposed 6bit CEBEC S15 [15] S14 [13] S13 [11] S 12 [9] S 11 [4] C10 [13] S05 [12] S04 [10] S03 [8] S02 [6] S01 [3] 5bit RCA (1) The group 5 of Fig. 8 consists of one 5-bit RCA comprising four FAs and one HA, when Cin = 0 . When Cin = 1 instead of using another 5-bit RCA or 6-bit BEC, a 6-bit proposed CEBEC adds one from the above 5-bit RCA. ...
... (3) Thus, we may note that the delays of the other groups depend only on the signal arrival time for multiplexer selection input and delay. (4) For group 5, the area count is determined with the following calculations: The group 5 of Fig. 10 or Fig. 5 consists of one 5-bit RCA when Cin = 0 , compris- [4] C12 [6] C13 [8] C14 [10] Cout [12] S15 [13] S14 [11] S13 [9] S12 [7] S 11 [4] C10 [12] Sum11 [16] Sum12 [16] Sum13 [16] Sum14 [16] Sum15 [16] Cout [14] CE [2] 10:5 Mux Content courtesy of Springer Nature, terms of use apply. Rights reserved. ...
This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based SQRT CSLA by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path to improve speed of operation, area and energy efficiency. The second proposed method is an optimized design of the regular SQRT CSLA by employing the carry enable and add-one ripple carry adder (ARCA) architectures to decrease the number of gates.
... Since the visual quality of the image does not change significantly for small errors in pixel intensity values, a number of approaches that use approximate computing for hardware implementation of digital image processing architectures are proposed in the literature. Approximate adders and multipliers for digital image processing are proposed in [9][10][11][12][13][14][15]. Median filters that use regular sorting and two-dimensional rank order based sorting are proposed in [16][17][18]. ...
... Area-efficient CSLA with gate-level modifications using binary to excess-one conversion (BEC) circuit is proposed in [15]. Approximate adders for image and signal processing applications are proposed in [9,10,[25][26][27][28]. Jothin [10] proposed error-tolerant CSLA (ET-CSLA) that demonstrates significant improvement in area compared to [15]. ...
... Approximate adders for image and signal processing applications are proposed in [9,10,[25][26][27][28]. Jothin [10] proposed error-tolerant CSLA (ET-CSLA) that demonstrates significant improvement in area compared to [15]. However, ET-CSLA shows high average error due to the approximation of full adder cells used in the least and MS part. ...
Approximate computing is a novel approach to design area‐efficient arithmetic units for portable error resilient applications. In this work, the authors have proposed a parallel architecture for median filter targeting digital image processing. Proposed parallel median filter (PMF) uses pre‐sorter and post‐merge units to replace corrupted processing pixel (PP) with a median of pixels in the 3X3 processing window. Approximate compare and swap (CS) blocks that can trade off area at the expense of accuracy are proposed and used in the proposed PMF. Two variants of PMF are realised based on the implementation of approximate CS units in the pre‐sorter and post‐merge blocks. In PMF‐design1, the authors use the exact CS unit in the pre‐sorter and approximate CS unit in the post‐merge block (hereafter referred to as P‐EA) and in PMF‐design2, they use approximate CS unit in both pre‐sorter and post‐merge blocks (hereafter referred to as P‐AA). Functionality and accuracy efficacy of the proposed PMFs are verified with the image de‐noising application. Synthesis with 90 nm application specific integrated chip technology revealed that to the least, proposed PMFs demonstrate 33.75 and 41.9% area‐delay product and power‐delay product reductions, respectively, compared to the standard median filter.
