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![Fig.5. New version of 14T [16].](profile/Deepak-Garg-10/publication/340807074/figure/fig1/AS:882620363726850@1587444501801/New-version-of-14T-16_Q320.jpg)
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The 1-bit full adder circuit is one of the most important components of any digital system applications. The power-delay product is a measurement of the energy expanded per operational cycle of an arithmetic circuit. This paper presents a new low power full adder based on a new logic approach, which reduces power consumption by implementing full ad...
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... logic circuit of the full adder is shown in figure 10. The OR gate can be realized using a wired OR logic. ...
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Citations
... However, dynamic full adders are faster and some times more compact than static full adders. Dynamic full adders suffer from charge sharing, high power due to high switching activity, clock load and complexity [6]. ...
... DG-8T [6] has been implemented a full adder is based on three transistor XOR gate and 2-to-1 multiplexer with 8 transistors in total is shown in fig.10. It acquires least silicon area. ...
The 1-bit full adder circuit is one of the most
commonly used extensively in many very large-scale
integration circuits such as application- specific digital
signal processing systems and microprocessors. An adder is
used for the overall analysis of the circuits in most of the
systems. This paper describes various types of full adders
based on different techniques for low power. All the
analysis is depends on some different simulation parameters
such as transistor count, delay, power-delay product, power
consumption, and the value of power supply. Each full
adder used different tool for the simulation purpose. The
various type of full adder circuit design are studied and
evaluated. This survey paper discussed various technologies
for low power. This paper is very useful for the circuit
designers to find the full adder as per the requirement of
their applications.
Background
This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs.
Methods
Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology.
Results
From the analysis result high performance full adder is extracted for the further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio.
Conclusion
From the analysis it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.
FA is basic cell for arithmetic operation and lots of efforts have put to minimize power consumption and delay. This paper evaluates conventional CMOS adder, bridge style adders in sub-threshold region. Circuits are designed at 20 MHz and 50 MHz frequencies with VDD= 200 mv. All adder designs are simulated at 32 nm technology. In 1 bit and 32 bit conventional CMOS adder design, an efficient trade-off between delay and power is achieved. Experimental results show that 32 bit adder designs have significant improvements in delay and power delay product.
