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![(Left) Cross-sectional view and (Right) top layout view of the 3D stacked NAND string. GSL and SSL are the BLS and SLS, respectively. CSL is the common source line. Reproduced with permission from [7]. c 2009 IEEE.](publication/319047767/figure/fig2/AS:526031657811968@1502427128918/Left-Cross-sectional-view-and-Right-top-layout-view-of-the-3D-stacked-NAND-string.png)
(Left) Cross-sectional view and (Right) top layout view of the 3D stacked NAND string. GSL and SSL are the BLS and SLS, respectively. CSL is the common source line. Reproduced with permission from [7]. c 2009 IEEE.
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Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in consumer and enterprise scenarios. To keep the evolutionary pace of the technology, NAND Flash mu...
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... [7], a two-layer 3D stacked NAND Flash built entirely from a planar process has been described, as shown in Figure 2. On the first layer (i.e., indicated as MAT1 in Figure 2 where MAT stands for matrix), the memory array and also the peripheral circuitry are present, whereas the second layer (MAT2) is only for the array. Metal bitlines contact both layers using vias. Since the bitlines are shared, the sensing can be performed with a minimal burden on the capacitive load; therefore, the only penalty in timings and power consumption is ascribed to the vias [17]. String decoders are independent, allowing safe operations in terms of layer disturbs. As pointed out earlier in the paper, this memory concept allows operating independently on each layer, although a proper biasing scheme is mandatory to avoid errors and reliability issues. Table 1 resumes the bias conditions of each layer for read, program and erase operations. The table assumes the architecture described in Figure 3 where MAT1 is the first layer that is currently selected for operation, MAT2 is the second layer, which is inhibited, BLn represents the shared bitline contact, BLS is the bitline selector, SLS is the source line selector, SL is the common source line contact and P-Well is the common p-doped silicon well bias for erase operation. [7,17]. BLn, shared bitline ...
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... [7], a two-layer 3D stacked NAND Flash built entirely from a planar process has been described, as shown in Figure 2. On the first layer (i.e., indicated as MAT1 in Figure 2 where MAT stands for matrix), the memory array and also the peripheral circuitry are present, whereas the second layer (MAT2) is only for the array. Metal bitlines contact both layers using vias. Since the bitlines are shared, the sensing can be performed with a minimal burden on the capacitive load; therefore, the only penalty in timings and power consumption is ascribed to the vias [17]. String decoders are independent, allowing safe operations in terms of layer disturbs. As pointed out earlier in the paper, this memory concept allows operating independently on each layer, although a proper biasing scheme is mandatory to avoid errors and reliability issues. Table 1 resumes the bias conditions of each layer for read, program and erase operations. The table assumes the architecture described in Figure 3 where MAT1 is the first layer that is currently selected for operation, MAT2 is the second layer, which is inhibited, BLn represents the shared bitline contact, BLS is the bitline selector, SLS is the source line selector, SL is the common source line contact and P-Well is the common p-doped silicon well bias for erase operation. [7,17]. BLn, shared bitline ...
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... second V-NAND generation has been introduced in 2015 by increasing the storage bit density from two bits/cell to three bits/cell [12]. Comparing with the previous generation, there were not many macroscopic changes in the memory cell structure, although the number of layers switched from 24 to 32. The bitlines layout is different as sketched in Figure 23. In this case, two bitlines are arranged in a single pillar pitch [12]. BL density is doubled (i.e., the NAND Flash page size step from 8 kB to 16 kB), but the number of contacts to the SL plate is halved. However, the overall number of pillars is the same as the first generation V-NAND. Another highlight of the second generation V-NAND is the so-called single-sequence programming.In this improved algorithm, the V-NAND asks for 3 NAND Flash pages at the start of the programming, and it writes the pages at once, turning into faster operations and lower power consumption. The third generation of V-NAND architecture became public in 2016 [13]. It is still a three bits/cell architecture, but this time, it is a 256-Gb product based on a stack of 48 layers. When the number of layers increases, the etching technology becomes a serious issue due to the aspect ratio of the pillar (see Figure 24). Therefore, the only solution is to reduce the layers' thickness with severe drawbacks on the wordline features like the parasitic resistance and capacitance. Moreover, as the parasitic resistance increases, the channel hole size fluctuations are even more important in the charge flow control across the wordline. An adaptive program pulse scheme per wordline is therefore applied to increase the overall reliability of the memory. The algorithm basically varies the program pulse duration according to the target wordline characteristics. The general scaling trend for every 3D NAND Flash technology is to increase the number of integrated layers. However, this has a negative impact on the geometry of the pillar (i.e., the aspect ratio) since it becomes longer. The compensation of such a layout degradation is visible in the fourth V-NAND generation [35], which exploits a 64-layer stack. In this architecture variant, the layer thickness and the intra-layer spacing shrinked, with adverse effects on the cell's reliability and timings. Improved programming algorithms and ad hoc circuits can be used to reduce the parasitic wordline capacitance effects derived by layer scaling ...
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... second V-NAND generation has been introduced in 2015 by increasing the storage bit density from two bits/cell to three bits/cell [12]. Comparing with the previous generation, there were not many macroscopic changes in the memory cell structure, although the number of layers switched from 24 to 32. The bitlines layout is different as sketched in Figure 23. In this case, two bitlines are arranged in a single pillar pitch [12]. BL density is doubled (i.e., the NAND Flash page size step from 8 kB to 16 kB), but the number of contacts to the SL plate is halved. However, the overall number of pillars is the same as the first generation V-NAND. Another highlight of the second generation V-NAND is the so-called single-sequence programming.In this improved algorithm, the V-NAND asks for 3 NAND Flash pages at the start of the programming, and it writes the pages at once, turning into faster operations and lower power consumption. The third generation of V-NAND architecture became public in 2016 [13]. It is still a three bits/cell architecture, but this time, it is a 256-Gb product based on a stack of 48 layers. When the number of layers increases, the etching technology becomes a serious issue due to the aspect ratio of the pillar (see Figure 24). Therefore, the only solution is to reduce the layers' thickness with severe drawbacks on the wordline features like the parasitic resistance and capacitance. Moreover, as the parasitic resistance increases, the channel hole size fluctuations are even more important in the charge flow control across the wordline. An adaptive program pulse scheme per wordline is therefore applied to increase the overall reliability of the memory. The algorithm basically varies the program pulse duration according to the target wordline characteristics. The general scaling trend for every 3D NAND Flash technology is to increase the number of integrated layers. However, this has a negative impact on the geometry of the pillar (i.e., the aspect ratio) since it becomes longer. The compensation of such a layout degradation is visible in the fourth V-NAND generation [35], which exploits a 64-layer stack. In this architecture variant, the layer thickness and the intra-layer spacing shrinked, with adverse effects on the cell's reliability and timings. Improved programming algorithms and ad hoc circuits can be used to reduce the parasitic wordline capacitance effects derived by layer scaling ...
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... V-NAND architecture proposed by Samsung in 2013 [29] is actually the first 3D NAND Flash concept brought to mass production, stemming from the initial work made on the development of the TCAT architecture. The official introduction to the market of the V-NAND dates back to 2014 [30,31], when a 128-Gb 2-bit/cell product embodied a damascened CT cell option (i.e., a SONOS memory cell) and 24 layers (see Figure 22). In this architecture, two dummy wordlines (i.e., dummy CG plates) are integrated close to the BLSs and SLSs. These additional structures are needed to shield the edge wordlines from the program disturb. Indeed, during program operation, high channel boosting potential may generate hot carriers at the string edges due to the high lateral electric field. This translates into program disturb and corruption of the threshold voltage distributions ...
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... 2009, Samsung proposed an alternative to the BiCS architecture, namely the Terabit Cell Array Transistor (TCAT) [16]. A view of the overall array organization is presented in Figure 19. From the electrical standpoint, the TCAT circuit scheme is the same as the BiCS scheme already presented in this paper, with a difference in the source plate. In TCAT, the SL lines are made by the n + -silicon diffusion shorted together to a common source line that is placed outside the cells array. Two metallization levels are deposited to decode the BLSs and CGs/SLS elements, respectively. To understand the peculiarities of the TCAT architecture, let us assume an example array with the configuration depicted in Figure 20. In the figure, we show two NAND Flash blocks each one constituted by seven wordlines and six CG layers. All of the wordlines are connected to the Metal1 level, so that with this metallization, it is possible to decode the NAND Flash strings, whereas with the additional Metal2 level, it is possible to decode the wordline. By comparing TCAT with BiCS, it is possible to observe that the blocks slit is visible as a cut in the bitline layer. Besides the difference in architectural elements of TCAT and BiCS structures, there are some significant technology replacements that should be investigated in the former architecture. TCAT uses an integration technique called gate-replacement [16], which is constituted by depositing the gate layer only in the last step of the stack manufacturing process. The BiCS architecture, on the contrary, exploits a gate-first approach. The former gate creation technology deposits several layers of silicon dioxide and sacrificial silicon nitride layers that are etched between each row of pillars. Dielectrics and metal gates are then deposited in the conventional order by filling the wordline space with tungsten. A final etching process will separate the CGs. The created memory cell is a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)-type, which provides advantages in terms of erase speed, data retention and threshold voltage distribution margins. Further, having a metal gate allows reducing the parasitic resistance of the wordline contact, thus meaning faster ...
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Memory devices based on floating-gate transistor have recently become dominant technology for non-volatile storage devices like USB flash drives, memory cards, solid-state disks, etc. In contrast to many communication channels, the errors observed in flash memory device use are not random but of special, mainly asymmetric, type. Integer codes which...
Citations
... As indicated by the characteristics of flash wear and tear described in 2.1, the objective of enhancing flash storage capacity cannot be achieved in an endless manner like logic chips, by scaling down the transistor components to increase storage density. Under the premise of not improving the process to ensure storage reliability, the use of 3D stacking technology to further increase the storage capacity per unit physical area has become a new trend [5]. Currently, the mainstream 3D stacking technologies [6], P-BiCS [7], VNAND [8], TCAT [9], and Xtacking from YMTC [10], among others. ...
Data storage devices are an important component of computer systems. Solid-state Drives, which use NAND Flash technology, are widely used in various fields due to their unique advantages such as high read-write speed, low power consumption, shock resistance, and small size compared to traditional mechanical hard drives. This paper first discusses the basic structure and principles of Flash memory, including floating gate transistors for storing and reading charges. Based on the current state of NAND Flash-based solid-state hard drives, this paper discusses key technologies and characteristics such as flash memory types, wear leveling, garbage collection, etc. It explores their features, advantages and limitations, and finally reasonably deduces the future development trend of Flash devices.
... Nanoscale fin-FETs 1-3) and 3D-NAND [4][5][6][7] cells have been applied to semiconductor devices to achieve high computing performance. Plasma etching is one of the key processes in fabricating these devices, and the number of etching parameters in plasma-etching tools has increased for nanoscale process control. ...
Machine learning was applied to optimize etching profile for line-and-space pattern sample in plasma etching. To investigate effect of difference of initial-learning dataset on optimization of etching profile, high-, medium-, and low-quality datasets were prepared. The high-quality dataset was composed of etching results relatively close to a target etching profile. The low-quality dataset was composed of etching results relatively far from the target etching profile. The medium-quality dataset was intermediate between the high- and low-quality dataset. For the machine learning, Kernel ridge regression method was used. After six learning cycles, better etching results were obtained by the medium- and low-quality datasets than to that in the whole initial-learning dataset. However, the etching results by the high-quality dataset did not exceed that in the whole initial-learning dataset. These results indicate that initial-learning dataset having etching results far from the target profile can be useful to optimize etching profile.
... 3D NAND flash memory device with increased data capability has become the mainstream of every platform which require data storage for applications of mobile devices [1]. With all its promising properties, however, the increasing stacking layers in order to increase data capacity also add many challenges not only for manufacturing process but also for basic understanding from fundamental point of view. ...
... Therefore, three-dimensional (3D) NAND devices, which are the latest rendition of NAND memory devices, have been the focal point of much research in the industry. 1,2 In the fabrication of 3D NAND memory devices, an alternating stack of films [e.g., silicon dioxide (SiO 2 ) and silicon nitride (SiN)] are deposited on a silicon wafer. To form the memory cells, hole channels must be etched through all the deposited films. ...
... An etching process to form HAR structures is referred to as HAR etching. [1][2][3] The typical ion incident energy of HAR etching for NAND device manufacturing is said to be several keV, possibly up to over 10 keV, although there has been little open discussion on the actual ion energies used in the industry. HAR etching is challenging because of the difficulty in maintaining the circular cross sections and straight-depth profiles of the holes' inner surfaces, upon which memory cells are built. ...
As the sizes of semiconductor devices continue to shrink, the fabrication of nanometer-scale device structures on material surfaces poses unprecedented challenges. In this study, molecular dynamics simulations of CF[Formula: see text] ion beam etching of SiO[Formula: see text] were performed with carbon masks to form holes with a diameter of 4 nm. It is found that, when the ion energy is sufficiently high and the etching continues, tapered holes are formed by the ion beam etching. This is because the etching under these conditions is essentially due to physical sputtering, so that tapered surfaces having high etching yields appear as the sidewalls and sputtered Si-containing species are redeposited. Furthermore, preferential removal of oxygen from SiO[Formula: see text] surfaces occurs, which leads to the formation of Si-rich sidewall surfaces. It is also found that, with simultaneous irradiation of CF[Formula: see text] radicals, the etching yield of a flat SiO[Formula: see text] surface by energetic CF[Formula: see text] ion beams can double, but too large a flux of CF[Formula: see text] radicals causes etch stop.
... Semiconductor devices with higher integration have been continuously developed to address the demand for high-speed information processing and communication. NAND flash memory technology [1][2][3][4] has been the leading solution to any platform that requires data storage. ...
Molecular dynamics simulations for the scattering of neon, argon, and xenon ions on silicon and silicon dioxide surfaces were performed at grazing incidence to examine how the angular distribution of reflected ions deviates from that of the ideal specular reflection, depending on the ion mass, incident angle, and surface material and its roughness. This study is motivated to understand how energetic ions interact with the sidewalls of high-aspect-ratio (HAR) channels when reactive ion etching (RIE) is used to form such HAR channels in semiconductor manufacturing. It is found that the higher the ion mass is, the less grazing the ion incident angle is, or the rougher the surface is, the larger the angular distribution of reflected ions becomes around the corresponding specular reflection angles. Quantitative information on such reflected ions can be used to predict the profile evolution of HAR channels in RIE processes.
... Therefore, the current 3D NAND industry is struggling with a double hardship in which it is necessary to improve various cell characteristics caused by small unit cell size and also improve the device performance. Thus far, one direction to address the above technology challenges is the development of new process integration and materials, and many review papers have reported on this [7][8][9]. However, there has been few reviews from the perspective of device operation techniques and algorithms, although many studies are being conducted. ...
The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.
... Recently, various structures of three dimensional NAND flash memory (3D NAND) such as TCAT, P-BICS, and VSAT have been introduced [1][2][3][4]. 3D NAND have contributed greatly to the capacity improvement of memory products. Compare with conventional 2D NAND devices, 3D NAND can realize higher integration and larger capacity with the same chip size. ...
Since the most of three dimensional (3D) NAND devices’ channel is composed of polysilicon grain, the actual 3D NAND channel has a wave-shaped channel, not uniform shape. In this study, we defined the curvature of the channel as a ’Wave Factor (WF)’ parameter, and simulated 3D NAND device with the WF applied channel. Various effects of the curvature in the channel on the program and erase operation of the device have been investigated. When the channel is wave-shaped, the electric field tends to be concentrated on the corner region of the blocking oxide during the program operation, which causes increase of the electron back tunneling to the gate. Therefore, program speed degraded as the WF value higher. During the erase operation, the same with program operation, the electric field concentrated on the corner of the blocking oxide increased, enhanced electron back tunneling from the metal gate occurred while less amount of hole charge trapped. As a result, VTH shift after the erase operation decreased according to increased WF. This phenomenon becomes more serious on the short channel condition. In addition, the result shows that degradation of erase characteristic by WF can be prevented by applying thicker blocking oxide.
... The two poly-Si channels in the structure share a common source line (CSL) formed by the WL cut. Figure 4b shows that the circuit diagram of the TCAT cell array is equivalent to that of a 90 • -rotated planar flash array per string layer, and its bottom end is connected to the CSL. The ground selection line (GSL) and string selection line (SSL) transistors are at the top and bottom of a string, respectively, and flash cells are placed between them in series [4,33]. Figure 5a shows the VRAT architecture containing a planarized-integration-on-thesame-plane (PIPE) structure for effective vertical interconnection [5]. ...
... Because the undercut process is not required for the VSAT structure, it is easy to realize vertical strings along with the stacked WLs, which are similar to the currently commercialized 3D NAND flash string. In addition, the dual-gate structure of the VSAT architecture effectively elongates the channel length without cell density loss, leading to a reduction in the off-current [5,[33][34][35]. ...
In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.
... The primary element of the array is the stack of Control Gates (CGs), also indicated as Layers. Associated with each CG, there are several wordlines that depend on the specific integration concept for the memory [17]. The bottom of the memory architecture is represented by the Source Line and the Source Line Selectors of the 3D NAND Flash string. ...
... This leads to a better control of the 3D NAND Flash reliability and in turn to a reduced system-level effort in coping with endurance and retention errors using complex error correction codes or secondary correction schemes. We also want to stress that, due to the different architectural and integration options of 3D NAND Flash technology [17], we expect that the RBER behavior may expose a different trend for memories manufactured with a different process/architecture with respect to that characterized in this work. However, our proposed randomization methodology is still foreseen to yield the same RBER improvements, while the HC randomizer will still evidence shortcomings in terms of the worst case RBER. ...
Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology. However, the paradigm change represented by the 3D memory integration concept has complicated the randomization task due to the increased dimensions of the memory array, especially along the bitlines. In this work, we propose an easy to implement, cost effective, and fully scalable with memory dimensions, randomization scheme that guarantees optimal randomization along the wordline and the bitline dimensions. At the same time, we guarantee an upper bound on the maximum length of consecutive ones and zeros along the bitline to improve the memory reliability. Our method has been validated on commercial off-the-shelf TLC 3D NAND Flash memory with respect to the Raw Bit Error Rate metric extracted in different memory working conditions.
... As an example to increase capacity and reduce bit costs of memory structures, multi-layer systems [15][16][17], as well as three-dimensional structures [18,19], were established. In order to connect the different planes of a multilayer memory structure in a microchip, so-called through-silicon vias (TSV) are used. ...
... A cross-section of the volume and enlarged sections of it are shown in c-e. Based on publicly available information, these structures are expected to be between 100-200 nm [15,16,23,45,46]. In the enlarged view (e), two additional structure sizes were determined from the image and also specified. ...
In a comprehensive study, we demonstrate the performance and typical application scenarios for laboratory-based nano-computed tomography in materials research on various samples. Specifically, we focus on a projection magnification system with a nano focus source. The imaging resolution is quantified with common 2D test structures and validated in 3D applications by means of the Fourier Shell Correlation. As representative application examples from nowadays material research, we show metallization processes in multilayer integrated circuits, aging in lithium battery electrodes, and volumetric of metallic sub-micrometer fillers of composites. Thus, the laboratory system provides the unique possibility to image non-destructively structures in the range of 170–190 nanometers, even for high-density materials.
