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In this paper a 10-bit 1.2-GSample/s Nyquist current-steering CMOS digital-to-analog converter (DAC) is presented. Segmentation
(90%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher
performance is achieved using a novel 3-D thermometer decoding method which reduces the area, po...
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Citations
... At first, the digital inputs are decoded into 1-D thermometercoded signals, and logic gates then act as the decision-maker according to the row and column locations whether the unit current source becomes on or off. 10,11 Also, in previous studies, 5,16,17 multidimensional decoders are presented, in which the input codes have been divided into more than two groups to decrease the conversion delay at the cost of a higher number of logic gates. Besides the mentioned decoder implementations, previous studies [18][19][20] introduce a new decoder design using multiplexers. ...
... For at least 99.5% INL yield, the ratio of the number of DAC with an INL less than one LSB to the total number of tested DAC, the value of C is 3.2. 26 Also, according to the Pelgrom model in, 27,28 the (σI/I) equation is defined as follows: Therefore, the (σI/I) value for the 10-bit DAC can be calculated as Equation 5: ...
This paper proposes a new 10‐bit 1GS/s digital‐to‐analog converter (DAC). In the proposed DAC configuration, a beneficial combination of differential resistor ladder and current sources is utilized to attain a significant reduction of the number of unit current sources. Therefore, the suggested 10‐bit DAC is constructed based on only 21 current sources and 64 unit resistors, which results in a considerable decrease regarding the occupied area and power consumption. Also, a modified 4‐bit thermometer decoder using a low number of transistors, based on SET‐RST D flip‐flops (SR‐DFFs), is offered to drive the unit current sources synchronously. The proposed DAC is simulated in 65‐nm Complementary metal oxide semiconductor (CMOS) technology. The postlayout simulation results indicate the better integral nonlinearity (INL) and differential nonlinearity (DNL) parameters than 0.3 least significant bit (LSB) and 0.6 LSB, respectively. Based on achieved results, the proposed DAC consumes 9.31 mW using a single supply voltage of 1.2 V. Moreover, the spurious‐free dynamic range (SFDR) is above 57 dB over 600‐MHz Nyquist bandwidth, by considering 0.0134 mm2 its occupied area.
... Among various DAC structures, current steering DACs are privilege structures due to their high speed and accurate operation [2][3][4]. Generally, current steering DACs are categorized into binary [5], unary [6], and segmented [7][8][9][10][11][12][13] structures. Binary DACs benefit from a simple structure with the metrics of the small number of switches, low power consumption, and small chip area. ...
... Therefore, physical and electrical mismatches are exhibited between identical devices on an integrated circuit. Current source mismatches generally affect the dynamic performance of the current steering DACs and result in random errors and systematic errors [6,14]. The simplest way to mitigate the random errors is to use large transistors for the unit current sources, but this comes at the cost of a larger chip area and an increase in the systematic error such as gradient error. ...
In this paper, a new 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology is presented. The new structure benefits from a combination of a resistor ladder and current sources. By using the resistor ladder, the identical current sources are weighted, which leads to remarkably reduce the number of current sources needed for realization a 10-bit DAC. Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 56 dB over 600 MHz Nyquist bandwidth. The INL and DNL parameters are also obtained better than 0.4 LSB. The proposed DAC dissipates just 7.49 mW power with a single supply voltage of 1.2 V. Also, the occupied area is 0.0071 mm2.
... Generally, current steering DACs are designed in the form of binary [5], unitary [6], or segment [7]. Binary DACs, in spite of small size, have a noticeable glitch and INL/DNL error, and cannot be used in high resolution structures [8]. ...
this brief presents a new 11-bit 1.2 GS/s hybrid digital to analog converter (DAC) simulated in 65 nm CMOS technology. In this new structure, a combination of a resistor ladder and current sources is used to realize the 11-bit DAC structure. The current sources are connected to different nodes of the resistor ladder in a logical way. In this situation, equal current sources make different voltage values. Furthermore, the complicated binary to thermometer decoders are exchanged with the basic digital logics. This new technique remarkably reduces the number of current sources needed for realization an 11-bit DAC and leads to the circuit dissipates just 4.68 mW power while the power supply is 1.2 V. Also, the occupied area is 0.0061 mm². Post layout simulation results indicate that the spurious-free dynamic range (SFDR) is more than 70 dB over 600 MHz Nyquist BW. The INL and DNL parameters are also obtained better than 1.2 LSB and 1 LSB, respectively.
... Later, in papers [5] and [6], the similar approach was discussed for 3 and 4 groups. Authors conclude that a multidimensional structure is faster and provide some estimations for area and power consumption, but these estimations don't allow us comparing decoders with each other. ...
... Moreover, because of employing the presented segmented structure, it has very high SFDR and very small INL. However, the sample rate of the presented DAC is lower than previous reports in [2,3,6,20,21] and the output swing is the lowest among other works in the table. In order to have a better comparison, four Figure of merits (FOMs) are used in Table 3. ...
In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-μW power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and VDD=0.9-V supply voltage with the sample rate of 140MS/s show SFDR > 64.37dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.
... In modern telecommunication systems such as mobile cellular phone and digital radio, current-steering digital to analog converters are used because of their high speed, high accuracy, optimum power consumption, relatively small chip area and compatibility with CMOS technology [1,2]. ...
... In segmented architecture which is chosen for the proposed DAC, input bits are subdivided into most significant bits (MSBs) and least significant bits (LSBs) [3]. The segmentation of digital input bits is intended to reach an optimum performance in terms of several factors including glitch energy, integral nonlinearity (INL) and differential nonlinearity (DNL) errors, monotonicity, control signal number, and area [1]. ...
... According to [3,5], in a 12-bit segmented current steering DAC, by dedicating 9 bits to thermometer codes and 3 bits to binary codes, the total area (digital and analog) will be minimized and besides, the best performance is achieved. The conventional 9-bit BT decoder in [1] has complexity in scheme, chip area and power consumption. In recent works such as [4,6], division of the codes into subgroups and consequently conversion of the subgroups into thermometer codes leads to much better results in cheap area and power consumption while deterioration in INL/DNL error, glitch energy and SFDR are took place in Nyquist rate. ...
A 12-bit 8-4 segmented current-steering digital to analog converter (DAC) is presented in this paper. The designed DAC consumes low power compared to similar designs. The number of control signals and chip area are also reduced considerably. High performance of the proposed DAC owes to appropriate segmentation of the digital input bits and employment of a new nested Binary to Thermometer (BT) decoder which uses domino logic gates. The proposed decoder is deployed in 3 similar stages with repetitive gates and pipelining scheme. Therefore, total power consumption of the DAC in 0.18 μm CMOS technology at the sample rate of 1 GHz is approximately 62 mWatt. The digital supply voltage is 1.2 V while the analog supply voltage is 1.8 V. In addition, over the output bandwidth of 500 MHz at 1GS/s, the spurious-free dynamic range (SFDR) reaches 60.8 dB.
... Requirements for meeting the desired SFDR performance of sampled signals close to the Nyquist rate will become more stringent because of the trade-off between the SFDR and sampling rate [3]. The degradation of the SFDR performance can be attributed to static and dynamic non-linearity [1], [4]. Static non-linearity arises from the mismatch between transistors, while dynamic non-linearity can be attributed to switching characteristics and finite output impedance of the current source cells [1]. ...
This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. The DAC is implemented using silicon–germanium (SiGe) BiCMOS 130 nm technology and achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in a much larger power dissipation.
... 1,2 Nowadays, high speed and high accuracy DACs are needed in modern telecommunication systems such as GSM and HDTV. 3 Among many DACs' structures, currentsteering architecture has low power consumption, small chip area, high speed, high accuracy and it is compatible with CMOS process. 3,4 The current-steering DAC has three main architectures: Binary weighted, unary weighted and segmented architecture. ...
... 1,2 Nowadays, high speed and high accuracy DACs are needed in modern telecommunication systems such as GSM and HDTV. 3 Among many DACs' structures, currentsteering architecture has low power consumption, small chip area, high speed, high accuracy and it is compatible with CMOS process. 3,4 The current-steering DAC has three main architectures: Binary weighted, unary weighted and segmented architecture. 2,5 The static performance of the DAC is speci¯ed through integral nonlinearity (INL) and di®erential nonlinearity (DNL). ...
... The advantages of this architecture are simplicity and small area, but glitch energy and INL/ DNL errors are large and monotonicity will not be guaranteed. 3,6 In unary weighted architecture, the binary code is converted to the thermometer code by means of BT decoder which it controls current cell array. This type of DAC has disadvantages of the large chip area and complexity, but low glitch energy, low INL/DNL error and monotonicity will be guaranteed with this architecture. ...
In this paper, a 10-bit 8-2 segmented current-steering digital to analog converter (DAC) is presented which uses a novel nested Binary to Thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in 3 stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18 μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mWatt while the digital and analog supply voltages are 1.2 V and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3mm2.
... Indrit and Ali [3] introduced a new swing reduced driver (SRD) circuit to serve as a gate driver for steering switches of high speed current steering DAC. Peiman and Nasser [4] presented another type of SRD circuit. Joo,Kim and Yoon [5] introduced a SRD circuit which minimizes clock feedthrough effect and prevents the degrading of the dynamic performances due to switching noise. ...
This work presents a glitch improved design of a 12-bit fully differential current source resistor string hybrid digital-to-analog converter (DAC) achieved by incorporating a swing reduced driver (SRD) circuit in the existing design. The results show that this design achieves a 13.26 % improvement in glitch reduction in comparison with the original version. The physical layout of the glitch improved design DAC is accomplished within a design area of 489.4 μm x 117 μm or 57260 µm^2 .
... A review of the circuit techniquesis explainedd asfollowsw. ( Indrit and Ali, 2009;Peiman and Nasser, 2009) 2 shows the concept of the switch core for low glitch DAC. The output of a decoder is synchronized through the latch block and then drives differential switches through a deglitch circuit and the Swing Reduced Driver (SRD). ...
... As a result, the charge injection to I OUT + and I OUT is decreased and the glitch energy is greatly reduced in the output current. Peiman and Nasser, 2009) presented a dummy approached to eliminate the glitches occurred because of the improper switching as shown in Fig. 11. Two dummy transistors are fabricated in the same sizes with the transistors in a differential pair to cancel out the feedthrough effects. ...
A state of the art of circuit techniques is presented focusing on the glitch reduction in current steering Digital to Analog Convert (DAC). Internal capacitance reduction, current source output impedance increment, source degenerated, dummy transistor for switch and switching core circuit techniques are reviewed.
