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SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSp...
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... layout of the SALT is presented in Figure 8. It has dimensions of 10.90 mm× 4.75 mm, where the horizontal dimension is driven by the pitch of the input pads (80 µm) matching the UT silicon sensor pad pitch. ...
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... has dimensions of 10.90 mm× 4.75 mm, where the horizontal dimension is driven by the pitch of the input pads (80 µm) matching the UT silicon sensor pad pitch. Inside the chip, signals are processed from the input pads (top in Figure 8) towards the serialiser and data drivers, placed near the back side (bottom in Figure 8). The top part of the layout contains 128 readout channels, oriented vertically, with analogue front-end and ADC, while the bottom section is almost purely digital, including the PLLs (3 rectangles at bottom-right) and DLL (rectangle at centre-left) circuits. ...
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... has dimensions of 10.90 mm× 4.75 mm, where the horizontal dimension is driven by the pitch of the input pads (80 µm) matching the UT silicon sensor pad pitch. Inside the chip, signals are processed from the input pads (top in Figure 8) towards the serialiser and data drivers, placed near the back side (bottom in Figure 8). The top part of the layout contains 128 readout channels, oriented vertically, with analogue front-end and ADC, while the bottom section is almost purely digital, including the PLLs (3 rectangles at bottom-right) and DLL (rectangle at centre-left) circuits. ...
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... it was decided to use one ASIC design for both hybrid types, the SALT layout must support two power supply schemes. For 4-chip hybrid the power supply is delivered symmetrically from the left and right sides (see Figure 8), while for 8-chip hybrid only from the back side. To keep a similar level of symmetry in both cases, the analogue part of the chip is divided into two 64-channel blocks, and the power supply is delivered centrally from the back side through the digital part of the chip and distributed in a star-like connection between the blocks. ...
Citations
... The UT modules are composed of the silicon sensors and the front end readout electronics, glued and bonded to dataflex cables [3]. The silicon micro strip sensors have been developed in 4 different types, employed depending on their position in the layer to cope with different occupancies. ...
... An ultra-low power ADC with a sampling rate of 40 MSps or more, medium-high resolution, and small pitch is required for multi-channel readout ASICs in modern and future LHC or other experiments. Recent developments of such complex readout ASICs are a 128-channel SALT ASIC for the LHCb Upstream Tracker, which contains an analogue front-end and a 6-bit 40 MSps ADC in each channel [1], or a 72-channel HGCROC ASIC for the CMS High Granularity Calorimeter, which contains an analogue front-end, a 10-bit 40 MSps ADC and a precision TDC in each channel [2]. In fact, a fast 10-bit ADC is one of the most requested and used blocks in the readout of various detector systems [2][3][4][5][6]. ...
The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.
... For applications in future particle physics detectors one of typical requirements regarding speed is a sampling frequency of at least 40 MHz, which corresponds to the beam crossing frequency in the world's largest accelerator, the Large Hadron Collider (LHC) at CERN [8]. Recently, the first 128-channel front-end ASIC containing a 6-bit ADC in each channel sampling at 40 MHz, has been developed for the readout of the Upstream Tracker subdetector of the LHCb experiment at CERN [9]. For various detector systems, e.g., calorimetry, a much higher amplitude resolution of 10 or even more bits is required. ...
The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed for multi-channel readout systems, in particular for applications in particle physics experiments, are discussed. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL<0.4 LSB, DNL<0.3 LSB) and dynamic (ENOB=9.45) measurements was performed to study and quantify the performance of ADC. The ADC converts analogue signals with a sampling frequency up to 55 MHz and power consumption below 1 mW. The ADC works asynchronously, so no external clock is required. The ADC Figure of Merit (FOM) at 50 MHz sampling frequency is 24 fJ/ conv.-step , and is the lowest among the State of the Art designs with similar technology and specifications.
... The UT employs four different sensor types to cope with the different occupancy, geometry, and radiation expected in the various regions of the detector. A dedicated 128 channels Application Specific Integrated Circuit (ASIC) called SALT (Silicon ASIC for LHCb Tracking) reads the incoming events from each sensor [3] [8]. A total of 4192 ASICs are mounted on flexible low mass polyamide circuits, called hybrids, providing power and digital signal routing. ...
We present a description of the design process, prototyping and production of the hybrid circuits for the front-end electronics of the Upstream Tracker at LHCb. The multilayer polyamide-based printed circuit boards, or hybrids, are designed to host the front-end ASICs. The ASICs require an optimized power delivery network from 0 to 120MHz, with a maximum of 10^-2 Ohms round-trip resistance, and 100 Ohms differential traces. Hybrids are required to have minimal radiation length, and to withstand the harsh environmental conditions of the data taking through intrinsic radiation hardness characteristics.
... The project evolved over time into two complementary ASICs: GBTX intended for fast data transmission [2] and GBT-SCA for detector control and monitoring [3]. GBT ASICs were used in many readout systems developed for phase I of the LHC upgrade, such as [4][5][6][7]. These chips were also used in the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR) [8]. ...
In this paper, the Low Power Giga Bit Transceiver (lpGBT) built-in system for environmental monitoring of the LHC experiments is presented. Eight external analogue inputs and eight internal voltages are multiplexed into an instrumentation amplifier with selectable gain, whose output is digitised by a 10-bit SAR ADC. A programmable current source can be enabled for each external input to implement resistance measurements. Internal channels are used to monitor power supplies and the output of the temperature sensor. The environmental monitoring system includes a precise 1 V reference voltage source and a 10-bit voltage DAC. All blocks were designed and fabricated in 65 nm CMOS technology, fully characterised, and the pre- and post-irradiation measurement results are presented in this work.
... The chip versions used in the UT are the SALTv3.5 for most of the 4-chip hybrids and the SALTv3.9 for the 8-chip hybrids and some of the most exposed 4-chip hybrids. More detailed information on the SALT ASIC can be found in Ref. [66]. ...
... The clock phase of each of the 32 channels of the FEB can be adjusted independently. 66 AD9238 from Analog Devices. ...
The LHCb upgrade represents a major change of the experiment. The detectors have been almost completely renewed to allow running at an instantaneous luminosity five times larger than that of the previous running periods. Readout of all detectors into an all-software trigger is central to the new design, facilitating the reconstruction of events at the maximum LHC interaction rate, and their selection in real time. The experiment's tracking system has been completely upgraded with a new pixel vertex detector, a silicon tracker upstream of the dipole magnet and three scintillating fibre tracking stations downstream of the magnet. The whole photon detection system of the RICH detectors has been renewed and the readout electronics of the calorimeter and muon systems have been fully overhauled. The first stage of the all-software trigger is implemented on a GPU farm. The output of the trigger provides a combination of totally reconstructed physics objects, such as tracks and vertices, ready for final analysis, and of entire events which need further offline reprocessing. This scheme required a complete revision of the computing model and rewriting of the experiment's software.
The LHCb upgrade represents a major change of the experiment. The detectors have been almost completely renewed to allow running at an instantaneous luminosity five times larger than that of the previous running periods. Readout of all detectors into an all-software trigger is central to the new design, facilitating the reconstruction of events at the maximum LHC interaction rate, and their selection in real time. The experiment's tracking system has been completely upgraded with a new pixel vertex detector, a silicon tracker upstream of the dipole magnet and three scintillating fibre tracking stations downstream of the magnet. The whole photon detection system of the RICH detectors has been renewed and the readout electronics of the calorimeter and muon systems have been fully overhauled. The first stage of the all-software trigger is implemented on a GPU farm. The output of the trigger provides a combination of totally reconstructed physics objects, such as tracks and vertices, ready for final analysis, and of entire events which need further offline reprocessing. This scheme required a complete revision of the computing model and rewriting of the experiment's software.
We present a description of the design process, prototyping and production of the hybrid circuits for the front-end electronics of the Upstream Tracker at LHCb. The multilayer polyamide-based printed circuit boards, or hybrids, are designed to host the front-end ASICs. The ASICs require an optimized power delivery network from 0 to 120 MHz, with a maximum of 10 ⁻² Ohms round-trip resistance, and 100 Ohms differential traces. Hybrids are required to have minimal radiation length, and to withstand the harsh environmental conditions of the data taking through intrinsic radiation hardness characteristics.
