Figure 4 - uploaded by Megha Agrawal
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Layout of PMOS V T extractor.

Layout of PMOS V T extractor.

Source publication
Conference Paper
Full-text available
This paper describes an input free MOS transistor circuit which provides ground referenced threshold voltage of PMOSFET on its output and consumes very low power. This VTP extractor is designed using the difference of gate-source voltages in two different size transistors carrying equal currents. The total power consumed by this VT extractor is 133...

Context in source publication

Context 1
... layout of this PMOS V T extractor shown in figure 4 was designed using Cadence Virtuoso layout editor. The layout has area 167.4 μm 2 . ...

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