Latch D implementation using floating-gate transistors

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... used as comparator. While the input FGMOS transistors process data, the p-MOS semi-latch ensures a valid output. If eventually the FGMOS transistors are turned off by inducing the appropriate offset to their floating gates, the last output data is stored by the p-MOS semi-latch until the next computation be carried. To achieve this process, a control gate is added to the FGMOS transistors. If this control gate is connected to ground, the weighted sum of input voltages will be too low to turn any of the FGMOS transistors on. According to the above, the D latch shown in Fig. 1 is proposed. While normal operation, SET and RST in- puts are normally set to 0. As these inputs have twice the weight of the rest of the inputs, the FGMOS transistors threshold voltage can only be reached when the clock input (Ck) is in a high state. If Ck and SET/RST inputs have a low state, no matter the state of the input D, both transistors will be off and the data at the outputs will be retained. If eventually Ck flips to a high state, the state of D will be large enough to trigger the latch. In the case that SET or RST has a high state, a change at the output will occur immediate- ly; as these inputs has twice the weight of the other inputs will override the state of D or Ck. To achieve the set or reset process, Ck needs to be low to avoid the possibility that both input FGMOS transistor be turned on simultaneously resulting in an invalid output. Due to their small transistor count, the proposed latch solve prob- lems as body effect; implementations as CMOS or pass-transistor latches uses long chains of series transistors, resulting in a degra- dation of the output data. To restore output noise, buffers can be used. Although this solution can effectively restore output levels, it will increase both power and delay of the gate. Whenever the clock input Ck has a high state, the first D latch will pass the input data to its output. If Ck flips to zero, the input data will be stored at the first latch. Simultaneously, the second D latch will pass the held data to the output Q. When Ck flips back to high, the first gate will admit a new input data while the output latch will be holding the last output state. Fig. 3 and Fig. 4. The latching operation is realized by two cross coupled inverters. The feedback of the inverters will make possible the data holding. To modify the stored data, pass- gate transistors at the input of each of the two D latches are used. When Ck have a high state, the first pass-gate will allow data acquisition by the first latch while isolate the second. If Ck chang- es to low, the first latch will hold the last input data, passing through the second latch to the output Q. When a Set/Rst proce- dure is carried out, the feedback loop between the latching invert- ers is opened. Once the feedback loop is open, the Set/Rst data is applied. When this procedure is finished, the feedback loop is restored. As well as the previous circuits, it consists in two D latches in series. This implementation requires five transistors in series, making the flip-flop to operate at very low frequency. Besides, the power requirement rises, making the imple- mentation not suitable for low voltage. The voltage re- quirement, the transistor tree height and the large count of transistors and switching nodes, makes this implementation improper for energy efficient battery driven applications Simulations were performed using SPICE with an ON- Semiconductors 0.5 ?m CMOS technology. To achieve realistic results, the technique discussed in (Rodriguez-Villegas, Huertas, Avedillo, Quintana and Rueda 2001) is employed for simulation of floating-gate transistors. For each of the implementations, a load similar to a flip-flop of the same family was used at the out- put. Fig. 5 shows the simulation results for all of the flip-flop im- plementations. Even when FGMOS and CMOS were able to work at lower voltage, the simulations were performed at 3.3 volts. The long transistor chain of CPL implementation was not able to work properly below this voltage By using a high gain amplifier as comparator, PFFGL is able to use the smallest transistors allowed by the technology. This condi- tion let using small input capacitances for the FGMOS transistors, achieving the smallest input capacitance of the comparison. The resulting input capacitance of the PFFGL flip-flop is less than 19 fF. Low voltage and small capacitance internal nodes allow PFFGL to show significant improvements in power characteristics. Fig. 6 is show an energy comparison between all the flip-flop implementations. CPL showed the worst case, consuming an amount of energy equal to 10.67 pJ along the test cycle. CMOS showed similar power characteristics, wasting 10.39 pJ along the cycle. The best power performance was reached by the PFFGL implementation, with a reduction of 28% in energy consumption resulting in an energy waste of 7.69 pJ. It was expected CMOS to have the worst performance in the comparison due to its large count of transistors and the long transistor trees. Even though, CPL resulted to be the worst case in voltage and power consump- tion. Table 1 shows the comparison of the three flip-flops. Can be seen that the floating gate flip-flop have the smaller transistor count in the comparison, requiring an area of 51 X 28 ?m2. Be- sides the area reduction due to a small transistor count, there is an improvement due to a simplification of routing. Smaller devices and simplified routing leads to improvements in circuit ...