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A 56-mW 23-mm<sup>2</sup> GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm<sup>2</sup> radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]°C temperature range. The r...
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Context 1
... with the DSP, the LNA sets a lower limit to the sen- sitivity of the system. It must be designed together with its ESD protection structures that typically worsen LNA performance. In Fig. 5, the CMOS LNA, the off-chip tuning inductor at the gate , the ESD structures and the parasitic capacitance at the input of - including the pad ( ) are depicted. As far as the LNA is concerned, a single stage with on-chip de- generation has been used for reduced power consumption and improved linearity. For sake of simplicity, the ...
Context 2
... at the gate , the ESD structures and the parasitic capacitance at the input of - including the pad ( ) are depicted. As far as the LNA is concerned, a single stage with on-chip de- generation has been used for reduced power consumption and improved linearity. For sake of simplicity, the impact of ESD structures (enclosed in dashed lines in Fig. 5) on input match and noise performances will be discussed later. The cascode configuration improves the reverse isolation and reduces the Miller capacitance at the input of - . A 7-nH differential on-chip inductor with a quality factor tunes the output of the LNA. The 50-input match is achieved with the combination of the on-chip ...
Context 3
... typical ESD protection structure consists of a series resis- tance between the protected pin and the bond wire pad, plus two diodes connected between the protected pin and both ground and supply. For noise reasons, series resistance cannot be in- troduced and the arrangement shown in Fig. 5 has been used: diodes at the inputs of the LNA and an additional active clamp connected between supply and ground. Due to the presence of ESD structures, the input impedance at resonance is reduced ac- cording to the following expression [2]: (4) where (5) With respect to the situation with , 50-match is achieved with a larger value of ...
Citations
... However, [7], [11] have used PPF. In the literature [23], [27] a combination of the CBPF and PPF is used. It will help to improve image rejection and increase the voltage gain of the entire circuit. ...
A fully integrated GPS receiver system can enable unique system capabilities by synthesizing both receiver front end and baseband on the same chip, leading to lower area overhead and higher integration. A survey on the GPS receiver system that focuses on front end design is presented in the paper. The first section discusses the various global navigation satellite system (GNSS), followed by the GPS working section. Afterwards, the paper discusses the previous works on the GPS receiver front end design. It provides a detailed survey and classification of various receiver architecture, including the LNA, mixer, filter, and ADC topologies. Besides, several image rejection techniques are presented for more than 50 GPS receivers. The various performance parameters of the GPS receiver front end in the literature are presented with the graphical view in the state-of-the-art discussion section. This literature survey provides the most extensive compilation to date of the various topologies, techniques and explains their implementation in the GPS receiver system. A new figure of merit that includes all the system parameters is proposed. The FOM can be an excellent reference to enhance the research work in the field of GPS receivers. In the end, the paper describes the possible research scope and challenges associated with the design of the GPS receiver front end.
... First of all, the GNSS receiver is stacked together with other receivers in smartphones (Bluetooth, WIFI, 3G) in one chip. The design of those chips has to face the problems of energy consumption and demand of miniaturization together with the performance of other functions (Gramegna et al. 2006;Kadoyama et al. 2004;Uvieghara et al. 2004). The review of papers indicates that currently the indoor positioning is more important than outdoor capabilities in cities. ...
Ever since field survey has become an important method in researching ancient communities we can observe improvement of its technological and theoretical aspects. Nowadays, rapid urban sprawl and intensified agriculture lead to the increasing destruction of sites and archaeological landscapes throughout the globe. Thus, an adequate low budget strategies is needed, that will able help to document, preserve, study and manage all what is left. The introduction of GIS and GNSS mobile applications opened a such possibility. At the 2017 CAA meetings in Atlanta, the authors organized a session entitled “Mobile GIS in ar- chaeology – current possibilities, future needs”, at which the current issues and possibilities were discussed. The session resulted in this summary paper. The main aim of the paper is to re-evaluate the contemporary concept of the survey that was introduced due to a rapid increase of GPS accuracy and development of mobile technology.
... Location-based services (LBS) utilizing GNSS positioning have become a part of everyday life. Nowadays, the LBS consumer market is dominated by single-frequency GPS (US global positioning system) C/A (coarse acquisition signal) only and low-cost, highly integrated GNSS receivers [3][4][5][6][7][8][9]. However, low precision and low reliability are their main limitations. ...
This work presents the results of research toward designing an instruction set extension dedicated to Global Navigation Satellite System (GNSS) baseband processing. The paper describes the state-of-the-art techniques of GNSS receiver implementation. Their advantages and disadvantages are discussed. Against this background, a new versatile instruction set extension for GNSS baseband processing is presented. The authors introduce improved mechanisms for instruction set generation focused on multi-channel processing. The analytical approach used by the authors leads to the introduction of a GNSS-instruction set extension (ISE) for GNSS baseband processing. The developed GNSS-ISE is simulated extensively using PC software and field-programmable gate array (FPGA) emulation. Finally, the developed GNSS-ISE is incorporated into the first-in-the-world, according to the authors' best knowledge, integrated, multi-frequency, and multi-constellation microcontroller with embedded flash memory. Additionally, this microcontroller may serve as an application processor, which is a unique feature. The presented results show the feasibility of implementing the GNSS-ISE into an embedded microprocessor system and its capability of performing baseband processing. The developed GNSS-ISE can be implemented in a wide range of applications including smart IoT (internet of things) devices or remote sensors, fostering the adaptation of multi-frequency and multi-constellation GNSS receivers to the low-cost consumer mass-market.
... The baseband processing power of this system is compared against other contemporary GPS receivers. The per channel baseband processing power in this system is about 3 times lower than the one in Ref. [54] and 12 times lower than the one in Ref. [55]. ...
Reducing the power consumption of modern digital CMOS integrated circuits (ICs) is one of the most critical design considerations. The prevailing synchronous ICs use global clocks to control the circuit operation, which causes a substantial amount of power consumed by the clock tree, as well as a series of timing issues that limit the effectiveness of many power reduction techniques. Asynchronous circuits, especially quasi-delay-insensitive (QDI) asynchronous circuits, use local handshaking protocols in lieu of clocks to coordinate circuit behavior. The delay insensitivity and other unique features of QDI circuits allow for more aggressive supply voltage scaling, implementing power gating without timing analysis or extra control overhead, connecting multiple components efficiently across a large die, and many other benefits for energy efficiency. This paper summarizes recent advances in low power QDI asynchronous circuit design, the status of EDA tool support, and some industry practices. In conclusion, while QDI asynchronous circuits have significant power saving potentials in many applications, efforts from researchers, designers, and EDA tool developers are needed to identify these applications, demonstrate the power advantage of QDI circuits, and alleviate the learning curve in automated QDI circuit design, in order for the semiconductor IC industry to more widely adopt QDI asynchronous logic in their products.
... Passive devices in general (resistors, capacitors, etc.) experience very few variations. In fact, published FEs with similar performances on different technology nodes have similar areas [20, 23, 24, 46] Furethermore, based on the discussion in section 1.6.2.3, the AC performance of the CMOS transistors improves in 65 nm as compared to 180 nm technology. This enables electronic circuits to have a higher operating frequency, which is of interest for RF circuitries such as LNAs, downconverters and synthesizers. ...
With the emergence of the new global navigation satellite systems (GNSSs) such as Galileo, COMPASS and GLONASS, the US Global Positioning System (GPS) has new competitors. This multiplicity of constellations will offer new services and a much better satellite coverage. Public regulated service (PRS) is one of these new services that Galileo, the first global positioning service under civilian control, will offers. The PRS is a proprietary encrypted navigation designed to be more reliable and robust against jamming and provides premium quality in terms of position and timing and continuity of service, but it requires the use of FEs with extended capabilities. The project that this thesis starts from, aims to develop a dual frequency (E1 and E6) PRS receiver with a focus on a solution for professional applications that combines affordability and robustness. To limit the production cost, the choice of a monolithic design in a multi-purpose 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology have been selected, and to reduce the susceptibility to interference, the targeted receiver is composed of two independent FEs. The first ASIC described here is such FEs bundle. Each FE is composed of a radio frequency (RF) chain that includes a low-noise amplifier (LNA), a quadrature mixer, a frequency synthesizer (FS), two intermediate frequency (IF) filters, two variable-gain amplifiers (VGAs) and two 6-bit flash analog-to-digital converters (ADCs). Each have an IF bandwidth of 50 MHz to accommodate the wide-band PRS signals. The FE achieves a 30 dB of dynamic gain control at each channel. The complete receivers occupies a die area of 11.5 mm2 while consuming 115 mW from a supply of a 1.8 V. The second ASIC that targets civilian applications, is a reconfigurable single-channel FE that permits to exploit the interoperability among GNSSs. The FE can operate in two modes: a ¿narrow-band mode¿, dedicated to Beidou-B1 with an IF bandwidth of 8 MHz, and a ¿wide-band mode¿ with an IF bandwidth of 23 MHz, which can accommodate simultaneous reception of Beidou-B1/GPS-L1/Galileo-E1. These two modes consumes respectively 22.85 mA and 28.45 mA from a 1.8 V supply. Developed with the best linearity in mind, the FE shows very good linearity with an input-referred 1 dB compression point (IP1dB) of better than -27.6 dBm. The FE gain is stepwise flexible from 39 dB and to a maximum of 58 dB. The complete FE occupies a die area of only 2.6 mm2 in a 0.18 µm CMOS. To also accommodate the wide-band PRS signals in the IF section of the FE, a highly selective wide-tuning-range 4th-order Gm-C elliptic low-pass filter is used. It features an innovative continuous tuning circuit that adjusts the bias current of the Gm cell¿s input stage to control the cutoff frequency. With this circuit, the power consumption is proportional to the cutoff frequency thus the power efficiency is achieved while keeping the linearity near constant. Thanks to a Gm switching technique, which permit to keep the signal path switchless, the filter shows an extended tuning of the cutoff frequency that covers continuously a range from 7.4 MHz to 27.4 MHz. Moreover the abrupt roll-off of up to 66 dB/octave, can mitigate out-of-band interference. The filter consumes 2.1 mA and 7.5 mA at its lowest and highest cutoff frequencies respectively, and its active area occupies, 0.23 mm2. It achieves a high input-referred third-order intercept point (IIP3) of up to -1.3 dBVRMS.
... Recent GPS radios employ single-conversion low-IF architecture to receive the narrow-band (typically 2.2 MHz) GPS signals [2], [3]. For the Galileo system, several radios have emerged that support both GPS and Galileo signals [4]- [6]. ...
A fully integrated dual-channel reconfigurable GNSS receiver supporting Compass/GPS/GLONASS/Galileo systems is implemented in 65 nm CMOS. The receiver incorporates two independent channels to receive dual-frequency signals simultaneously. GNSS signals located at the 1.2 GHz or 1.6 GHz bands are supported, with their bandwidths programmable among 2.2 MHz, 4.2 MHz, 8 MHz, 10 MHz, and 18 MHz. By implementing a flexible frequency plan with a low/zero-IF architecture and reconfigurable analog baseband circuits, only one frequency synthesizer is required to provide the local oscillator (LO) frequency for two channels, thereby avoiding any LO crosstalk. Analog baseband circuits employ operational amplifiers that are capable of power scaling, in order to minimize power consumption across different operating modes. An I/Q mismatch calibration module placed prior to the complex-IF bandpass filter is implemented to improve the image rejection ratio. The receiver achieves a minimum 1.88 dB noise figure, an average 50 dB image rejection ratio, and a 64 dB dynamic range with 1 dB steps of gain-adjustment, with a total power consumption of 31-44 mW. Finally, experimental verification combining both the receiver and a digital baseband shows a positioning result comparable to commercial chips.
... Traditionally, GPS radios adopted single conversion low-IF architecture to realize a narrow band GPS signal receiving [1]- [2]. In order to improve the accuracy, dual-channel radios began to emerge, including dual-conversion technique [3] and two frequency synthesizers for dual channel [4]. ...
A fully-integrated dual-channel reconfigurable GNSS receiver supporting GPS/Compass/Galileo/GLONASS in 65nm CMOS is presented. The receiver has two independent channels to support simultaneous dual-frequency reception, and can be reconfigured to receive various GNSS signals located in 1.2GHz or 1.57GHz band, which have different signal bandwidth including 2.2MHz, 4.2MHz, 8MHz, 10MHz and 18MHz. By flexible frequency plan, low-IF/zero-IF architecture switching and flexible analog baseband circuits, only one frequency synthesizer is adopted to provide local oscillation (LO) for two channels simultaneously, which could avoid the LO crosstalk issue. Analog baseband circuits employ operational amplifiers capable of power scaling to optimize power consumption among various mode operations. Besides, an I/Q mismatch calibration module placed ahead of the IF complex bandpass filter is implemented to improve image rejection ratio. The receiver finally achieves 2.2dB noise figure, an average of 50dB image rejection ratio, and 64dB dynamic range with 1dB gain-adjusting steps, while consuming a minimum of 31mW power.
... The VCO phase noise measurement has been performed injecting a RF signal at -50dBm (by a very low noise signal generator) into the RFA input and monitoring the IF analog signal measuring the down-converted phase noise. (2) 20mW @1.8V (2) 23mW (3) (1) LNA and RFA connected through external matching net; (2) without LNA; (3) Connecting LNA output and RFA input through proper matching network Next step: ...
... The VCO phase noise measurement has been performed injecting a RF signal at -50dBm (by a very low noise signal generator) into the RFA input and monitoring the IF analog signal measuring the down-converted phase noise. (2) 20mW @1.8V (2) 23mW (3) (1) LNA and RFA connected through external matching net; (2) without LNA; (3) Connecting LNA output and RFA input through proper matching network Next step: ...
... The VCO phase noise measurement has been performed injecting a RF signal at -50dBm (by a very low noise signal generator) into the RFA input and monitoring the IF analog signal measuring the down-converted phase noise. (2) 20mW @1.8V (2) 23mW (3) (1) LNA and RFA connected through external matching net; (2) without LNA; (3) Connecting LNA output and RFA input through proper matching network Next step: ...
In this paper, we present a low-power RF front-end designed for L1/E1 GPS/Galileo, implemented on 65 nm CMOS technology. It draws 16mA on external voltage supply of 1.2V, with power consumption of less than 20mW. The chip could work also at 1.8V using a low dropout regulator embedded in the chip. The device integrates a high performance low noise amplifier, an AGC that don't need any external capacitor and a PLL loop filter reducing the external components count: only few passives for matching and external TCXO for frequency reference are needed. A programmable synthesizer manages most of the commonly used TCXO frequencies. Two default operative modes and related reference frequencies have been defined: 16.368MHz and 26MHz. The IF filter is fully embedded. It is a complex filter characterized from two operative modes: the first for GPS-only signal, the second for both GPS and GALILEO signals. Its characteristics can be adjusted through a proper switching cascade of adaptive first order cells. The data bit for base band are generated by a 3-bits ADC. The whole die area is 2.6mm2
... Parameter Ref. [2] Ref. [12]* Ref. [13] Ref. [14] ...
... Although the power of the synthesizers in Refs. [12] [13] [14] is smaller than that in this work, the phase noise and spur are less attractive . Additionally, the synthesizers in Refs. ...
... Additionally, the synthesizers in Refs. [12] [14] were manufactured with expensive technology, and the power of that in Ref. [13] is not including the LO generator (high speed divide- by-2) and LO buffers to the quadrature mixer. The phase noise at 1 MHz offset in Ref. [2] is superior to ours, but its in-band phase noise is worse, and the power and area of the whole RF receiver are larger to some extent. ...
A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 m CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscil-lator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of –87 dBc/Hz at 15 kHz offset, with spurs less than –65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 .
... The power consumption of the Global Positioning System (GPS) receiver presented by Gramegna et al. [21] is in a middle position, when compared with the other receivers listed in Table 2. The explanation for such behaviour is because this type of receivers must present very high sensitivities; thus, a compromise between the power consumption and the LNA's gain must be achieved or the sensitivity will not target the specification [20]. ...
This paper presents radio-frequency (RF) microsystems (MSTs) composed by low-power devices for use in wireless sensors networks (WSNs). The RF CMOS transceiver is the main electronic system and its power consumption is a critical issue. Two RF CMOS transceivers with low-power and low-voltage supply were fabricated to operate in the 2.4 and 5.7 GHz ISM bands. The measurements made in the RF CMOS transceiver at 2.4 GHz, which showed a sensitivity of −60 dBm with a power consumption of 6.3 mW from 1.8 V supply. The measurements also showed that the transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The RF CMOS transceiver at 5.7 GHz has a total power consumption of 23 mW. The target application of these RF CMOS transceivers is for MSTs integration and for use as low-power nodes in WSNs to work during large periods of time without human operation, management and maintenance. These RF CMOS transceivers are also suitable for integration in thermoelectric energy scavenging MSTs.
