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In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the addit...
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... This has slowed down or even stopped the supply and threshold voltages reduction of transistors. For large chips, nowadays, leakage current could be similar to the switching current [46]. In summary, the leakage current is an essential factor that limits the step of scaling as it is threshold voltage-dependent. ...
The most crucial growth driver for the semiconductor industry is transistors downscaling.
Consequently, for decades, circuits have become denser and more complex, following a continuous trend with every new technology node (further scaling).
Previously, transistor scaling was always accompanied by supply voltage reduction to reduce power consumption, thus maintaining a constant power density.
Entering the nanometer era has slowed down the scaling process due to many difficulties (e.g., physical limitations) and the non-ideality in voltage scaling, leading to increased power density.
This has aggravated many reliability issues.
Transistor aging phenomenon, excessive temperature, and self-heating effect are few examples of such issues.
Conventionally, to mitigate these issues and sustain a reliable operation, timing guardbands have to be pessimistically considered, individually for every degradation effect, on top of the circuit's delay, to compensate for the induced delay degradations. This severely \textit{degrades the overall performance}.
However, mitigation can be alternatively achieved by applying substitutional techniques such as zero-temperature coefficient, approximate computing, etc.
Even though these techniques can eliminate or greatly reduce the large timing guardbands, further consequences and trade-offs may be encountered.
Difficulties limiting the scaling of CMOS technology continue to challenge. These limitations and the corresponding technological challenges are currently dictating a shift in research from CMOS technology to that of emerging technologies.
For instance, the Negative Capacitance Field-Effect Transistor (NCFET) is an emerging technology that has great potential to replace CMOS technology since NCFET exhibits considerable improvements in circuits' performance.
Additionally, designers switched to complex models by employing parallel processing modules instead of higher frequencies.
Such complex models necessitate advanced power management techniques at all design levels. These techniques must be revisited with new technology nodes, especially with emerging technologies, such as NCFET, where dependencies might change.
This dissertation presents novel approaches to solving these challenges on multiple design levels, providing techniques for analyzing and modeling circuit reliability and low-power design. Techniques are categorized into conventional ((a), (b), (c), and (d)), and unconventional techniques ((e), and (f)) as follows:
(a)
Analysis performance gains accompanied with maximizing energy efficiency when operating in the near-threshold region, specifically at optimal energy point. Finding accurately such a point for multicore design is challenging as it changes following the optimization goals and workload as well.
(b)
Revealing hidden interdependencies between transistor aging and voltage fluctuation caused by IR-drops.
Hence, a novel technique is presented, avoiding under-/over-estimation of timing guardbands, considering these interdependencies towards the smallest, yet sufficient, guardband estimation.
(c)
Towards containing transistor aging effects by employing graceful approximation technique, by making circuits faster only on-demand.
Aging timing guardband is supplanted by employing approximate computing.
The quantization technique is employed as a novel mechanism to maintain accuracy.
(d)
Towards containing thermal-induced delay degradation through operating circuits near Zero-Temperature Coefficient (N-ZTC).
Operating at N-ZTC minimizes thermal-induced variances in performance and power.
Qualitative and quantitative comparisons are presented against traditional timing guardband.
(e)
Modeling NCFET-aware power and energy management techniques for NCFET-based processors.
NCFET technology has unique properties, that differ from CMOS technology, which makes traditional DVS and DVFS suboptimal.
Hence, NCFET-aware power and energy management techniques are indispensably required, which are presented in this dissertation.
(f)
Introducing a novel heterogeneous manycore design in NCFET. Such design employs only identical cores. Heterogeneity can be achieved by efficiently employing the optimal configurations.
Extending Amdahl's law covering the execution of several new system-specific and application-specific parameters to quantify the benefits of the new design.
Evaluations of the proposed techniques are conducted through implementations and simulations at the circuit level (gate level) using the industrial chip design flow. Additionally, system-level simulators are used to implement and simulate manycore designs.
The validation and quantification of the effectiveness of these techniques against state of the art are done through analytical, gate-level, and system-level simulations covering synthetic and real applications.
... These unsolicited leakage currents should be reduced for the smooth functioning of the circuits. LECTOR Technique [6][7][8] is the technique to reduce leakage power consumption [9] in CMOS circuits without affecting the dynamic power [10]- [11] of the circuit.In this paper, the performance of parallel addersubtractor implemented with NAND gates using LECTOR technique is compared to the basic model and power dissipation and delay are compared. The fundamental building blocks of digital systems are logic gates. ...
With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles.The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors (HTLCT). In this paper; we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The proposed technique overcomes the limitations posed by the existing methods for leakage reductions an average leakage reductions is 82.5%. The estimation of power and delay will be discussed using LCT’s and HTLCT’s. © 2019 Institute of Advanced Engineering and Science. All rights reserved.
... These unsolicited leakage currents should be reduced for the smooth functioning of the circuits. LECTOR Technique [6][7][8] is the technique to reduce leakage power consumption [9] in CMOS circuits without affecting the dynamic power [10][11] of the circuit. In this paper, the performance of parallel adder-sub-tractor implemented with NAND gates using LECTOR technique is compared to the basic model and power dissipation and delay are compared. ...
... These unsolicited leakage currents should be reduced for the smooth functioning of the circuits. LECTOR Technique [6][7][8] is the technique to reduce leakage power consumption [9] in CMOS circuits without affecting the dynamic power [10][11] of the circuit. In this paper, the performance of parallel adder-sub-tractor implemented with NAND gates using LECTOR technique is compared to the basic model and power dissipation and delay are compared. ...
With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors (HTLCT).In this paper; we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The proposed technique overcomes the limitations posed by the existing methods for leakage reductions an average leakage reductions is 82.5%.The estimation of power and delay will be discussed using LCT’s and HTLCT’s.
... In non-conducting state, there are three types of leakage currents which are subthresold leakage current, gate induced drain leakage current and punch through current. [2] In conducting state two leakage currents are gate tunnelling current and junction leakage current. All leakage currents are shown in fig -2. ...
... As mentioned in [2] it may require extra circuitry to regenerate a specific input vector through some means on wake up mode. To maintain logic during sleep mode, the leakage feedback technique uses two additional transistors and the two transistors are driven by the output of an inverter which is driven by output of the circuit implemented utilizing leakage feedback [3]. Performance degradation and increase in area are the limitations along with the limitation of sleep technique. ...
The paper describes the approach to designing built-in monitoring buffers for the purpose of checking the functionality of ASICs as parts of test printed boards. A figure of merit (FOM), based on that analysis is suggested. Features of the FOM, applied to particle physics experiments, are the speed, power consumption, load driving capability and occupied chip area.
As an example, illustrating the choice of buffer according to the proposed FOM, there are presented the results of designing a buffer version as part of an ASIC for the CBM MUCH(http://www.fair-center.eu/for-users/experiments/cbm.html).
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A newtechnique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamicpower dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with thereduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuitis performed with extremely low leakage current as well as high current driving capability for the largeinput voltages. The proposed paper is achieved very high speed with very low propagation delay rangei.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by24% (in ns) at 3V square wave input. The measured quiescent current is 41μA.
