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Interaction between high-level and micro-level instruction scheduling.  

Interaction between high-level and micro-level instruction scheduling.  

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Figure 3: Pseudo code for building an FU-FSA for an Itanium ® processor.
Figure 5: Interaction between high-level and micro-level instruction...
Figure 6: Pseudo code for IssueOp using FU-FSA.  
Figure 10 compares the code size of the four configurations by...
+1 Figure 11: Cycle breakdown for crafty, eon, bzip2 and perlbmk.  
Efficient Modeling of Itanium® Architecture during Instruction Scheduling using Extended Finite State Automata
Article
Full-text available
  • Apr 2004
Effective and efficient modeling and management of hardware resources have always been critical toward generating highly efficient code in optimizing compilers. The instruction templates and dispersal rules of the Itanium® architecture add new complexity in managing resource constraints to instruction scheduler. We extended a finite state automaton...
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... a FU-FSA based micro-level scheduler taking care of the resource management, the instruction scheduler can focus on high-level scheduling decision. Figure 5 The instruction scheduler repeatedly picks the best candidate from a list of instructions in the schedule region that are ready for execution at the current cycle. The schedule region could be a simple basic block in a basic block scheduler. ...

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Compiler generation in PEAS-III: An ASIP development system
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A compiler generation method in PEAS-III is proposed in this paper. PEAS-III is an ASIP (Application Specific Instruction set Processor) development environment, which accepts processor specification including hardware resources and clock-based micro-operation description of instructions, and generates data path and control logic description of the...
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